Lines Matching +full:armada +full:- +full:8 +full:k +full:- +full:gpio
1 Marvell Armada AP80x System Controller
4 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
34 - #clock-cells: must be set to 1
37 --------
40 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
43 - compatible must be "marvell,ap806-pinctrl",
51 mpp0 0 gpio, sdio(clk), spi0(clk)
52 mpp1 1 gpio, sdio(cmd), spi0(miso)
53 mpp2 2 gpio, sdio(d0), spi0(mosi)
54 mpp3 3 gpio, sdio(d1), spi0(cs0n)
55 mpp4 4 gpio, sdio(d2), i2c0(sda)
56 mpp5 5 gpio, sdio(d3), i2c0(sdk)
57 mpp6 6 gpio, sdio(ds)
58 mpp7 7 gpio, sdio(d4), uart1(rxd)
59 mpp8 8 gpio, sdio(d5), uart1(txd)
60 mpp9 9 gpio, sdio(d6), spi0(cs1n)
61 mpp10 10 gpio, sdio(d7)
62 mpp11 11 gpio, uart0(txd)
63 mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
64 mpp13 13 gpio
65 mpp14 14 gpio
66 mpp15 15 gpio
67 mpp16 16 gpio
68 mpp17 17 gpio
69 mpp18 18 gpio
70 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
72 GPIO:
73 -----
75 Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
79 - compatible: "marvell,armada-8k-gpio"
81 - offset: offset address inside the syscon block
85 - marvell,pwm-offset: offset address of PWM duration control registers inside
89 ap_syscon: system-controller@6f4000 {
90 compatible = "syscon", "simple-mfd";
94 compatible = "marvell,ap806-clock";
95 #clock-cells = <1>;
99 compatible = "marvell,ap806-pinctrl";
102 ap_gpio: gpio {
103 compatible = "marvell,armada-8k-gpio";
106 gpio-controller;
107 #gpio-cells = <2>;
108 gpio-ranges = <&ap_pinctrl 0 0 19>;
109 marvell,pwm-offset = <0x10c0>;
110 #pwm-cells = <2>;
119 --------
128 critical point to any subnode of the thermal-zone node.
131 - compatible: must be one of:
132 * marvell,armada-ap806-thermal
133 - reg: register range associated with the thermal functions.
136 - interrupts: overheat interrupt handle. Should point to line 18 of the
137 SEI irqchip. See interrupt-controller/interrupts.txt
138 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
144 ap_syscon1: system-controller@6f8000 {
145 compatible = "syscon", "simple-mfd";
148 ap_thermal: thermal-sensor@80 {
149 compatible = "marvell,armada-ap806-thermal";
151 interrupt-parent = <&sei>;
153 #thermal-sensor-cells = <1>;
158 ---------------
165 - compatible: must be one of:
166 * "marvell,ap806-cpu-clock"
167 * "marvell,ap807-cpu-clock"
168 - #clock-cells : should be set to 1.
170 - clocks : shall be the input parent clock(s) phandle for the clock
173 - reg: register range associated with the cluster clocks
175 ap_syscon1: system-controller@6f8000 {
176 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
179 cpu_clk: clock-cpu@278 {
180 compatible = "marvell,ap806-cpu-clock";
182 #clock-cells = <1>;