Lines Matching +full:dma +full:- +full:requests
1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
40 operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in
44 hardware. AIC100 provides 3, 64-bit BARs.
48 * The second BAR is 2M in size, and exposes the DMA Bridge interface to the
54 From the host perspective, AIC100 has several key hardware components -
59 * DMA Bridge
63 ---
67 with the QSM. Except for workload data via the DMA Bridge, all interaction with
71 ---
74 firmware of the card and performs on-card management tasks. It also
79 ---
89 DMA Bridge
90 ----------
92 The DMA Bridge is custom DMA engine that manages the flow of data
93 in and out of workloads. AIC100 has one of these. The DMA Bridge has 16
95 workload is assigned a single DMA Bridge channel. The DMA Bridge exposes
100 ---
102 AIC100 has on-card DDR. In total, an AIC100 can have up to 32 GB of DDR.
106 requests to the QSM to transfer data to the DDR.
108 High-level Use Flow
111 AIC100 is a multi-user, programmable accelerator typically used for running
119 2. Make requests to the QSM to load the workload and related artifacts into the
122 4. Make requests to the DMA Bridge to send input data to the workload to be
123 processed, and other requests to receive processed output data from the
128 sessions, make requests to the QSM to unload the data from DDR. This frees
166 --------
169 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100-cc
172 ---------------------
175 https://github.com/quic/software-kit-for-qualcomm-cloud-ai-100
178 -------------
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235 DMA Bridge
239 --------
241 The DMA Bridge is one of the main interfaces to the host from the device
243 assigns that network a DMA Bridge channel. A workload's DMA Bridge channel
276 ------------
280 .. code-block:: c
309 sequence ID within a request. Ignored by the DMA Bridge.
312 describes the DMA element of this request.
314 * Bit(7) is the force msi flag, which overrides the DMA Bridge MSI logic
316 configures the DMA Bridge to look at this bit.
318 * Bit(4) is the completion code flag, and indicates that the DMA Bridge
345 * Bits(1:0) contain the encoding of the doorbell length. 0 is 32-bit,
346 1 is 16-bit, 2 is 8-bit, 3 is reserved. The doorbell address
357 * Bit(30) is the to-device DMA fence. Block this request until all
358 to-device DMA transfers are complete.
359 * Bit(29) is the from-device DMA fence. Block this request until all
360 from-device DMA transfers are complete.
370 semaphore operation is done after the DMA transfer. 1 is
371 presync, which gates the DMA transfer. Only one presync is
381 2. If enabled, the DMA transfer occurs
387 requests of data for the workload to process, but the DMA Bridge will only copy
392 -------------
397 .. code-block:: c
408 status of this request. 0 is success. Non-zero is an error.
410 The DMA Bridge will generate a MSI to the host as a reaction to activity in the
411 response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation
413 from empty to non-empty (unless force MSI is enabled and triggered). In
421 The NNC protocol is how the host makes requests to the QSM to manage workloads.
429 aligned. Since there are 64-bit elements in some NNC messages, 64-bit alignment
436 message N. This is used for exceedingly large DMA xfer transactions.
439 ------------------------
447 DMA transfer. Describes an object that the QSM should DMA into the
465 Continuation of a previous DMA transfer. If a DMA transfer
491 multi-stage recovery process is then used to cleanup both sides, and get the
496 remain in on-card DDR, but the host will need to re-activate the workload if