Lines Matching refs:InVec0

6276   SDValue InVec0 = DAG.getUNDEF(VT);  in LowerToAddSub()  local
6329 if (InVec0.isUndef()) { in LowerToAddSub()
6330 InVec0 = Op0.getOperand(0); in LowerToAddSub()
6331 if (InVec0.getSimpleValueType() != VT) in LowerToAddSub()
6342 if (InVec0 != Op0.getOperand(0)) { in LowerToAddSub()
6349 if (InVec0 != Op0.getOperand(0)) in LowerToAddSub()
6361 if (AddFound && SubFound && !InVec0.isUndef() && !InVec1.isUndef()) in LowerToAddSub()
6362 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1); in LowerToAddSub()
6392 SDValue InVec0, InVec1; in LowerToHorizontalOp() local
6395 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6396 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6398 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6399 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6402 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6403 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6405 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6406 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6416 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) && in LowerToHorizontalOp()
6418 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && in LowerToHorizontalOp()
6420 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6422 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) && in LowerToHorizontalOp()
6424 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && in LowerToHorizontalOp()
6426 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6433 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) && in LowerToHorizontalOp()
6435 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && in LowerToHorizontalOp()
6438 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) && in LowerToHorizontalOp()
6440 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && in LowerToHorizontalOp()
6450 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6461 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false, in LowerToHorizontalOp()
6469 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6471 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6473 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6475 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1)) in LowerToHorizontalOp()
6489 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true, in LowerToHorizontalOp()
21827 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops); in ReplaceNodeResults() local
21831 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1); in ReplaceNodeResults()