Lines Matching refs:Bit
1184 // SPR Bit set.
1194 // GPR Bit set.
1204 // GPRwithAPSR Bit set.
1214 // SPR_8 Bit set.
1224 // GPRnopc Bit set.
1234 // rGPR Bit set.
1244 // hGPR Bit set.
1254 // tGPR Bit set.
1264 // GPRnopc_and_hGPR Bit set.
1274 // hGPR_and_rGPR Bit set.
1284 // tcGPR Bit set.
1294 // tGPR_and_tcGPR Bit set.
1304 // CCR Bit set.
1314 // GPRsp Bit set.
1324 // hGPR_and_tcGPR Bit set.
1334 // DPR Bit set.
1344 // DPR_VFP2 Bit set.
1354 // DPR_8 Bit set.
1364 // GPRPair Bit set.
1374 // GPRPair_with_gsub_1_in_rGPR Bit set.
1384 // GPRPair_with_gsub_0_in_tGPR Bit set.
1394 // GPRPair_with_gsub_0_in_hGPR Bit set.
1404 // GPRPair_with_gsub_0_in_tcGPR Bit set.
1414 // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1424 // GPRPair_with_gsub_1_in_tcGPR Bit set.
1434 // GPRPair_with_gsub_1_in_GPRsp Bit set.
1444 // DPairSpc Bit set.
1454 // DPairSpc_with_ssub_0 Bit set.
1464 // DPairSpc_with_dsub_2_then_ssub_0 Bit set.
1474 // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1484 // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1494 // DPair Bit set.
1504 // DPair_with_ssub_0 Bit set.
1514 // QPR Bit set.
1524 // DPair_with_ssub_2 Bit set.
1534 // DPair_with_dsub_0_in_DPR_8 Bit set.
1544 // QPR_VFP2 Bit set.
1554 // DPair_with_dsub_1_in_DPR_8 Bit set.
1564 // QPR_8 Bit set.
1574 // DTriple Bit set.
1584 // DTripleSpc Bit set.
1594 // DTripleSpc_with_ssub_0 Bit set.
1604 // DTriple_with_ssub_0 Bit set.
1614 // DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
1624 // DTriple_with_qsub_0_in_QPR Bit set.
1634 // DTriple_with_ssub_2 Bit set.
1644 // DTripleSpc_with_dsub_2_then_ssub_0 Bit set.
1654 // DTriple_with_dsub_2_then_ssub_0 Bit set.
1664 // DTripleSpc_with_dsub_4_then_ssub_0 Bit set.
1674 // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
1684 // DTriple_with_dsub_0_in_DPR_8 Bit set.
1694 // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
1704 // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
1714 // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
1724 // DTriple_with_dsub_1_in_DPR_8 Bit set.
1734 // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set.
1744 // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
1754 // DTriple_with_dsub_2_in_DPR_8 Bit set.
1764 // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
1774 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
1784 // DTriple_with_qsub_0_in_QPR_8 Bit set.
1794 // DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set.
1804 // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
1814 // DQuadSpc Bit set.
1824 // DQuadSpc_with_ssub_0 Bit set.
1834 // DQuadSpc_with_dsub_2_then_ssub_0 Bit set.
1844 // DQuadSpc_with_dsub_4_then_ssub_0 Bit set.
1854 // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
1864 // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
1874 // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
1884 // DQuad Bit set.
1894 // DQuad_with_ssub_0 Bit set.
1904 // DQuad_with_ssub_2 Bit set.
1914 // QQPR Bit set.
1924 // DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
1934 // DQuad_with_dsub_2_then_ssub_0 Bit set.
1944 // DQuad_with_dsub_3_then_ssub_0 Bit set.
1954 // DQuad_with_dsub_0_in_DPR_8 Bit set.
1964 // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
1974 // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
1984 // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
1994 // DQuad_with_dsub_1_in_DPR_8 Bit set.
2004 // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
2014 // DQuad_with_dsub_2_in_DPR_8 Bit set.
2024 // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
2034 // DQuad_with_dsub_3_in_DPR_8 Bit set.
2044 // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
2054 // DQuad_with_qsub_0_in_QPR_8 Bit set.
2064 // DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set.
2074 // DQuad_with_qsub_1_in_QPR_8 Bit set.
2084 // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
2094 // QQQQPR Bit set.
2104 // QQQQPR_with_ssub_0 Bit set.
2114 // QQQQPR_with_dsub_2_then_ssub_0 Bit set.
2124 // QQQQPR_with_dsub_5_then_ssub_0 Bit set.
2134 // QQQQPR_with_dsub_7_then_ssub_0 Bit set.
2144 // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
2154 // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
2164 // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
2174 // QQQQPR_with_dsub_6_in_DPR_8 Bit set.