56203843 | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add runtime tx/rx antenna switch support to driver |
11d048d9 | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Re-structure/define drv reg idx. Add (drv) RF reg |
d3ce582a | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add the missing sdrctl reg category |
b196f496 | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add priv->actual_tx_lo preparing for further tx/rx related setting |
2ae501ca | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Disable TID in sdr.c:
By default the TID is disabled in FPGA, because we currently try to TX and RX traffic for all TIDs. So, the TID related operations in sdr.c are removed. |
0b4b8cc7 | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add all Europe 5GHz channel support into driver |
6a9949ee | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Replace some constants of number of NIC by MAX_NUM_VIF |
61a63978 | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add sysfs file based driver/FPGA access interface |
7d0af6df | 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Move sdrctl testmode cmd out to sdrctl_intf.c |
8dc97f7f | 26-Mar-2022 |
Xianjun Jiao <[email protected]> |
Avoid the git_rev.h issue:
When user download the repo instead of clone it. |
ce40e055 | 26-Mar-2022 |
Xianjun Jiao <[email protected]> |
Add modified ad9361_conv.c of our own: Sometimes the unstable hardware can not pass the 61.44Msps self-test/calibration. Override it to 40Msps |
9cd584f8 | 06-Jan-2022 |
mmehari <[email protected]> |
Missing aggregation rules |
385339ab | 06-Jan-2022 |
mmehari <[email protected]> |
tx_interrupt if/else optimization |
0c0d5d82 | 06-Jan-2022 |
mmehari <[email protected]> |
use FPGA fifo count registers instead of software queue_cnt |
c0981124 | 06-Jan-2022 |
mmehari <[email protected]> |
bug fixes: 1) update start_idx and blk_ack_ssn variables, 2) revert printing switch 3) update use_short_gi type (bool -> u8), 4) advance skb->tail by num_byte_pad for non aggregation flow |
2d12c07d | 06-Jan-2022 |
mmehari <[email protected]> |
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type |
f738aefa | 06-Jan-2022 |
mmehari <[email protected]> |
A-MPDU tx aggregation support |
261bb9ee | 06-Jan-2022 |
mmehari <[email protected]> |
A-MPDU rx aggregation support |
abdb610f | 20-Oct-2021 |
Jiao Xianjun <[email protected]> |
Scripts are adapted for SW HW decouple
To avoid openwifi-hw github submodule in openwifi. More flexible now. |
72c90e5e | 13-Oct-2021 |
Jiao Xianjun <[email protected]> |
Merge pull request #104 from open-sdr/fix_large_ping_delay_igent
Fix the issue of iGent env related big ping delay: |
b60e485e | 04-Oct-2021 |
Xianjun Jiao <[email protected]> |
Fix the possible wrong last_auto_fpga_lbt_th saving: 1. Remove the last_auto_fpga_lbt_th saving from sdrctl set reg command. Otherwise, repeated sdrctl set reg will save wrong value into last_auto_fp
Fix the possible wrong last_auto_fpga_lbt_th saving: 1. Remove the last_auto_fpga_lbt_th saving from sdrctl set reg command. Otherwise, repeated sdrctl set reg will save wrong value into last_auto_fpga_lbt_th 2. The last_auto_fpga_lbt_th is only set in ad9361_rf_set_channel, which is called at least once by Linux after NIC is up
show more ...
|
109b1cfd | 29-Sep-2021 |
Xianjun Jiao <[email protected]> |
Fix the issue of iGent env related big ping delay: 1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard 2. The issue does not happen when zcu102 is client and zedb
Fix the issue of iGent env related big ping delay: 1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard 2. The issue does not happen when zcu102 is client and zedboard is AP 3. The issue (most likely) does not happen in places other than iGent (like Pablo home) 4. Sometimes it does happen at my home when I test zcu102 as AP together with COTS WiFi 5. Indeed seems like the environment related. Guess some quick small packets in the environment quickly flush/round-up/mess-up the rx dma cyclic buffer, and the rx interrupt internal static variable target_buf_idx_old loses track of the background automatic rx dma cyclic buffer 6. The fix is for all board types (zcu102, zedboard, 7035, etc) 7. The driver compiling make_all.sh script generates USE_NEW_RX_INTERRUPT macro to pre_def.h to enable the new code (while keeping the old code). You can use the script as before. 8. The logic of the fix is that exhaustive search all the rx dma cyclic buffer in rx interrupt to get packet to Linux in the first place.
show more ...
|
8598d294 | 28-Sep-2021 |
Xianjun Jiao <[email protected]> |
Use drv_xpu register 0 for LBT threshold setting. 0 will enable FPGA threshold auto setting by ad9361_rf_set_channel() in sdr.c. Other value will set static threshold (that value) to FPGA |
d14d06e5 | 13-May-2021 |
Xianjun Jiao <[email protected]> |
CSI fuzzer feature -- document to be finished |
7cf9ba6e | 10-May-2021 |
Xianjun Jiao <[email protected]> |
Add dmesg printing option for broadcasting packet |