fix(FPGADiffDefaultConfig): set WithNKBL1D ways as default (#4237)

submodule(ready-to-run): Bump ready-to-run

* NEMU commit: 38697535806c21e3be5cf86a8c37062362fbaf1e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs

submodule(ready-to-run): Bump ready-to-run

* NEMU commit: 38697535806c21e3be5cf86a8c37062362fbaf1e
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
* riscv64-xs-ref-debug_defconfig
* riscv64-dual-xs-ref-debug_defconfig

Including:
* fix(aia): external interrupt priority from CLINT or IMSIC

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submodule(difftest): bump difftest

* commit: 16bb4f35a18c0a5b6d84e866f12263262dc2ab5e

Including:
* fix(wiring): return source only when not using source annotation (#554)
* fix(aia): distinguish ex

submodule(difftest): bump difftest

* commit: 16bb4f35a18c0a5b6d84e866f12263262dc2ab5e

Including:
* fix(wiring): return source only when not using source annotation (#554)
* fix(aia): distinguish external interrupts sources from CLINT or IMSIC (#556)

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fix(csr, difftest): distinguish external interrupts sources from PLIC or IMSIC

fix(csr): external interrupt priority from PLIC or IMSIC

fix(aia): iprio array is masked by xie CSR

* For a given interrupt number, if the corresponding bit in mie
is read-only zero, then the interrupt’s priority number in the
iprio array must be read

fix(aia): iprio array is masked by xie CSR

* For a given interrupt number, if the corresponding bit in mie
is read-only zero, then the interrupt’s priority number in the
iprio array must be read-only zero as well.

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timing(L2Top, XSTile): core-SoC signals should go through L2Top (#4222)

fix(Config): add the 'L3CacheCtrl' address space permission back (#4235)

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
-

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
- Disable clock gating in ICacheDataArray to improve timing

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timing(ittage): optimize the timing of the ittage path for reading the jump address (#4216)

fix(DCache): remove error wakeup signal for atomic resp (#4224)

The existence of `s2/s3_req.miss` in `atomic_resp_valid` will cause an
error resp to AtomicsUnit by a normal refill_req from MissQueue

fix(DCache): remove error wakeup signal for atomic resp (#4224)

The existence of `s2/s3_req.miss` in `atomic_resp_valid` will cause an
error resp to AtomicsUnit by a normal refill_req from MissQueue. Remove
it now to fix the problem.

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submodule(CoupledL2): fix assertion of Poison (#4220)

fix(IFU): remove useless bpu override flush logic (#4210)

When an override occurs in BPU S3 stage, the corresponding req can at
most reach the IFU F0 stage.

timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we sho

timing(ICache): move mshr_resp selector 1 cycle ahead (#4173)

> we can latch mshr.io.resp.bits since they are set on req.fire or
acquire.fire, and keeps unchanged during response
> however, we should not latch mshr.io.resp.valid, since io.flush/fencei
may clear it at any time

Old:
```
tilelink.resp.id -> | Reg |
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

New:
```
tilelink.resp.id
|
v
| MSHR0 | -> | --- |
| MSHR1 | -> | Mux | -> | Reg | -> io.resp
| ... | -> | |
| MSHRn | -> | --- |
```

Timing results are good, related path: slack -44ps -> positive.

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feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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fix(LSU): fix cbo instruction exception handling logic (#4215)

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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fix(AtomicsUnit): atomic access on uncache should raise af (#4214)

Atomic access on uncache or MMIO region is not supported for now. The
previous design did not consider exception handling for atomi

fix(AtomicsUnit): atomic access on uncache should raise af (#4214)

Atomic access on uncache or MMIO region is not supported for now. The
previous design did not consider exception handling for atomic
instructions with PBMT=NC.

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timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic to the previous cycle.

---

**Timing issue caused by long exception logic of load writeback to
`VLMergeBuffer`:**
- Add one cycle to the load writeback exception, now the same number of
cycles as the load write back data.

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timing(MemBlock): add 1 latch for hc_perfEvents (#4205)

timing(VSegmentUnit): duplicate latchVAddr (#4209)

* `latchVAddr` needs to index all dcache data sram from top to bottom,
which causes a large fanout, so duplicate `latchVaddr`

timing(LoadUnit, StoreUnit): remove redirect for out (#4207)

* remove useless cancel logic for writeback valid

fix(MainPipe): fix bug in data select of AMOCAS.Q (#4213)

Data selection logic should use signals in `s3` instead of `s1`, which
is introduced in a former pr #4117.

fix(MainPipe): use s3_tag_error to generate error report signal (#4208)

fix(L2TLB): reset tlbCounter when flush (#4202)