fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the Tl

fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)

Currently, only the CHI version of XS supports the CBO instruction , so
we are adding the illegal instruction to the TlieLink version of XS.

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'de

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'dest after rename,
which cause stalls.

In this commit, we set src2 in uop0 and dest in uop1, avoiding stalls by
renaming.

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feat(FTB, FTQ): split FTB meta SRAM and FTQ meta SRAM (#4360)

FTB meta SRAM: 512 × 320 -> (512 × 40) × 8
FTQ meta SRAM: 64 × 320 -> (64 × 160) × 2

fix(LoadUnit): fix misalign exception and clearer uncache semantics (#4426)

The loadAddrMisaligned exception is generated when misaligned accesses
uncache space.

---

A misaligned load sets a loadA

fix(LoadUnit): fix misalign exception and clearer uncache semantics (#4426)

The loadAddrMisaligned exception is generated when misaligned accesses
uncache space.

---

A misaligned load sets a loadAddrMisaligned exception at the s0 flag to
ensure that it only enters the loadmisalignbuffer and has no other side
effects.
So it will prevent s2_uncache from spawning properly.
Previously we used an additional `s2_un_misalign_exception` to flag
this.
Now, after examining the semantics of s2_uncache, the semantics of
s2_uncache can be appropriately represented by directly removing the
excepiont related signals

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fix(MainPipe): `error` and `writeback` addr generate logic (#4394)

There were errors in the previous design

* `writeback` generate wrong addr
* `writeback`'s addr use `s3_tag` to generate , no

fix(MainPipe): `error` and `writeback` addr generate logic (#4394)

There were errors in the previous design

* `writeback` generate wrong addr
* `writeback`'s addr use `s3_tag` to generate , no need to use
`s3_tag_error` to select.

* `error` generate wrong addr
* `error` must use `s3_tag` to generate, not use `s3_req.addr`,
* because the enable condition of `s3_req.addr` is different from that
of `s3_error`,
* should use access cacheline corresponding address

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feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoo

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoop.
* low-power process is controlled by FSM to follow the steps: flush L2
-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)
* SoC plays as PPU to generate power on/off sequence with signals:
isolation/reset/clock, also the power on/off req/ack signals

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fix(DM): synchronize the `jtag_reset` in standaloneDM (#4414)

fix(csr, difftest): do not update difftest framework on reset

fix(uncache): if can merge, it can enter even if buffer is full (#4408)

fix(L2TLB): Napot entries in LLPTW should not be compressed (#4396)

fix(PTWCache): Should refill full GVPN to Page Cache (#4407)

fix(PTW): High bits of GVPN should not be truncated (#4406)

fix(LLPTW): Fix exception judgement for different virtualisation stages (#4404)

In the previous exception handling in LLPTW, both isAf and isGpf were
checked for all cases, including allStage, onlyS

fix(LLPTW): Fix exception judgement for different virtualisation stages (#4404)

In the previous exception handling in LLPTW, both isAf and isGpf were
checked for all cases, including allStage, onlyStage1, and noS2xlate.

In fact, for allStage, only isPf & isGpf needs to be checked, while for
onlyStage1 and noS2xlate, only isPf & isAf should be checked.

This commit fixes this issue.

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fix(Top): fix `l3Miss` interface connection (#4410)

feat(ITTage,Tage): split ITTage SRAM and Tage SRAM (#4376)

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg
inOrder.

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fix(reidrectGen): fix redirectGen valid signal (#4392)

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all th

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all the information in a
single cycle for comparison with the parameters of sfence/hfence. As a
result, for L2 TLB entries, we ignored the rs1/rs2 parameters passed by
sfence/hfence and instead flushed all valid entries, regardless of
asid/vmid or vaddr.

However, this caused unnecessary flushing of a large number of entries
during process switching in virtualized environments, leading to L2 TLB
misses after a process switch. This forced the processor to perform a
page table walk in memory again, negatively impacting performance.

In this commit, asid/vmid and vaddr are hashed and stored in the
register file. When an sfence/hfence signal is received, these stored
values are compared against the incoming parameters, allowing for a more
precise TLB flush.

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fix(MMU): Unify latency in different CSR bundles (#4389)

In the previous design, since we don't flush pipeline after modifying
`satp`, we need to set whether or not increase the delay for different

fix(MMU): Unify latency in different CSR bundles (#4389)

In the previous design, since we don't flush pipeline after modifying
`satp`, we need to set whether or not increase the delay for different
signals in the csr bundle, such as priv and satp, respectively.

Currently, CSR will add send redirect signal to refresh the pipeline
after modifying `satp`, so we can unify latency in different CSR bundles
to fenceDelay.

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fix(vfalu): fix bug of allFFlagsEn, when vm is all zero flags should be zero (#4380)

fix(MainPipe): `DCache` meta is not changed when sc/cas fails (#4217)

`sc` miss are treated as failures directly and are no longer sent to the
`missqueue`.
The meta is no longer updated when `sc` fa

fix(MainPipe): `DCache` meta is not changed when sc/cas fails (#4217)

`sc` miss are treated as failures directly and are no longer sent to the
`missqueue`.
The meta is no longer updated when `sc` fail.

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fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m

fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m_resendTLB` etc..

Also:
- remove `currentIsRVC` as it's actually identical with `mmio_is_RVC`
- fix `crossPageIPFFix`, it should be valid only when `mmio_has_resend`
- rename `mmio_resend_exception` to `mmio_exception`, since it's also
used to store Tilelink corrupt before resend

Update: rebased to Feb-28-2025-66e9b546 for regression test.

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fix(Bitmap): Fix early `s_llptw_req` trigger in PTW (#4375)

- When `HasBitmapCheck` is enabled in `CVMConfig`.
- PTW module checks whether a bitmap check(`whether_need_bitmap_check`)
is needed after

fix(Bitmap): Fix early `s_llptw_req` trigger in PTW (#4375)

- When `HasBitmapCheck` is enabled in `CVMConfig`.
- PTW module checks whether a bitmap check(`whether_need_bitmap_check`)
is needed after receiving a `mem.resp` . then set `s_llptw_req` to be
valid and send a request to LLPTW.
- However, the `s_llptw_req` signal becomes valid one cycle too early.

Co-authored-by: LMiao <[email protected]>

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fix(L2TLB): fix `hptw_bypassed` wrong used in `refill_valid` (#4366)

The Reg `hptw_bypassed` is used to indicate a hptw's mem response no
need to refill PTWCache.
So add condition `from_hptw(mem.d.b

fix(L2TLB): fix `hptw_bypassed` wrong used in `refill_valid` (#4366)

The Reg `hptw_bypassed` is used to indicate a hptw's mem response no
need to refill PTWCache.
So add condition `from_hptw(mem.d.bits.source)` for `hptw_bypassed` used
in `refill_valid`,
to fix bug of Reg `hptw_bypassed` wrongly killing refill request from
another ptw.

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