| hw_def.h (913a9e947c549848c83acfc3a94293a22b007681) | hw_def.h (d14d06e5084df99af212b85724238a1d243b1b4a) |
|---|---|
| 1// Author: Xianjun jiao, Michael Mehari, Wei Liu 2// SPDX-FileCopyrightText: 2019 UGent 3// SPDX-License-Identifier: AGPL-3.0-or-later 4 5const char *sdr_compatible_str = "sdr,sdr"; 6 7enum openwifi_fpga_type { 8 SMALL_FPGA = 0, --- 13 unchanged lines hidden (view full) --- 22// ------------------------------------tx interface---------------------------------------- 23const char *tx_intf_compatible_str = "sdr,tx_intf"; 24 25#define TX_INTF_REG_MULTI_RST_ADDR (0*4) 26#define TX_INTF_REG_MIXER_CFG_ADDR (1*4) 27#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 28#define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 29#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) | 1// Author: Xianjun jiao, Michael Mehari, Wei Liu 2// SPDX-FileCopyrightText: 2019 UGent 3// SPDX-License-Identifier: AGPL-3.0-or-later 4 5const char *sdr_compatible_str = "sdr,sdr"; 6 7enum openwifi_fpga_type { 8 SMALL_FPGA = 0, --- 13 unchanged lines hidden (view full) --- 22// ------------------------------------tx interface---------------------------------------- 23const char *tx_intf_compatible_str = "sdr,tx_intf"; 24 25#define TX_INTF_REG_MULTI_RST_ADDR (0*4) 26#define TX_INTF_REG_MIXER_CFG_ADDR (1*4) 27#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 28#define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 29#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) |
| 30#define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) | 30#define TX_INTF_REG_CSI_FUZZER_ADDR (5*4) |
| 31#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 32#define TX_INTF_REG_MISC_SEL_ADDR (7*4) 33#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 34#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 35#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 36#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4) 37#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4) 38#define TX_INTF_REG_BB_GAIN_ADDR (13*4) --- 27 unchanged lines hidden (view full) --- 66 u32 (*reg_read)(u32 reg); 67 void (*reg_write)(u32 reg, u32 value); 68 69 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 70 u32 (*TX_INTF_REG_MIXER_CFG_read)(void); 71 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 72 u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void); 73 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); | 31#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 32#define TX_INTF_REG_MISC_SEL_ADDR (7*4) 33#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 34#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 35#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 36#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4) 37#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4) 38#define TX_INTF_REG_BB_GAIN_ADDR (13*4) --- 27 unchanged lines hidden (view full) --- 66 u32 (*reg_read)(u32 reg); 67 void (*reg_write)(u32 reg, u32 value); 68 69 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 70 u32 (*TX_INTF_REG_MIXER_CFG_read)(void); 71 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 72 u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void); 73 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); |
| 74 u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); | 74 u32 (*TX_INTF_REG_CSI_FUZZER_read)(void); |
| 75 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 76 u32 (*TX_INTF_REG_MISC_SEL_read)(void); 77 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 78 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 79 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 80 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void); 81 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void); 82 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 83 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 84 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 85 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void); 86 u32 (*TX_INTF_REG_PKT_INFO_read)(void); 87 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 88 89 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 90 void (*TX_INTF_REG_MIXER_CFG_write)(u32 value); 91 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 92 void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 93 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); | 75 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 76 u32 (*TX_INTF_REG_MISC_SEL_read)(void); 77 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 78 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 79 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 80 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void); 81 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void); 82 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 83 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 84 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 85 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void); 86 u32 (*TX_INTF_REG_PKT_INFO_read)(void); 87 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 88 89 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 90 void (*TX_INTF_REG_MIXER_CFG_write)(u32 value); 91 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 92 void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 93 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); |
| 94 void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); | 94 void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value); |
| 95 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 96 void (*TX_INTF_REG_MISC_SEL_write)(u32 value); 97 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 98 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 99 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 100 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value); 101 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value); 102 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); --- 303 unchanged lines hidden --- | 95 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 96 void (*TX_INTF_REG_MISC_SEL_write)(u32 value); 97 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 98 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 99 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 100 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value); 101 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value); 102 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); --- 303 unchanged lines hidden --- |