SimTop.scala (4b40434cb8e9fec610aad0fda0e437863b2716ec) SimTop.scala (2993c5ecece73b73073301e23435ca1b763d0b5f)
1/***************************************************************************************
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9* http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import org.chipsalliance.cde.config.Parameters
21import chisel3._
22import chisel3.util._
23import chisel3.experimental.dataview._
22import device.{AXI4MemorySlave, SimJTAG}
23import difftest._
24import device.{AXI4MemorySlave, SimJTAG}
25import difftest._
26import freechips.rocketchip.amba.axi4.AXI4Bundle
24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
25import utility.{ChiselDB, Constantin, FileRegisters, GTimer}
26import xiangshan.DebugOptionsKey
27
28class SimTop(implicit p: Parameters) extends Module {
29 val debugOpts = p(DebugOptionsKey)
30
31 val l_soc = LazyModule(new XSTop())
32 val soc = Module(l_soc.module)
33 // Don't allow the top-level signals to be optimized out,
34 // so that we can re-use this SimTop for any generated Verilog RTL.
35 dontTouch(soc.io)
36
37 l_soc.module.dma.get <> 0.U.asTypeOf(l_soc.module.dma.get)
38
39 val l_simMMIO = LazyModule(new SimMMIO(l_soc.socMisc.get.peripheralNode.in.head._2))
40 val simMMIO = Module(l_simMMIO.module)
27import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
28import utility.{ChiselDB, Constantin, FileRegisters, GTimer}
29import xiangshan.DebugOptionsKey
30
31class SimTop(implicit p: Parameters) extends Module {
32 val debugOpts = p(DebugOptionsKey)
33
34 val l_soc = LazyModule(new XSTop())
35 val soc = Module(l_soc.module)
36 // Don't allow the top-level signals to be optimized out,
37 // so that we can re-use this SimTop for any generated Verilog RTL.
38 dontTouch(soc.io)
39
40 l_soc.module.dma.get <> 0.U.asTypeOf(l_soc.module.dma.get)
41
42 val l_simMMIO = LazyModule(new SimMMIO(l_soc.socMisc.get.peripheralNode.in.head._2))
43 val simMMIO = Module(l_simMMIO.module)
41 l_simMMIO.io_axi4 <> soc.peripheral.get
44 l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.get.viewAs[AXI4Bundle]
42
43 val l_simAXIMem = AXI4MemorySlave(
44 l_soc.misc.memAXI4SlaveNode,
45 16L * 1024 * 1024 * 1024,
46 useBlackBox = true,
47 dynamicLatency = debugOpts.UseDRAMSim
48 )
49 val simAXIMem = Module(l_simAXIMem.module)
45
46 val l_simAXIMem = AXI4MemorySlave(
47 l_soc.misc.memAXI4SlaveNode,
48 16L * 1024 * 1024 * 1024,
49 useBlackBox = true,
50 dynamicLatency = debugOpts.UseDRAMSim
51 )
52 val simAXIMem = Module(l_simAXIMem.module)
50 l_simAXIMem.io_axi4.getWrappedValue :<>= soc.memory.waiveAll
53 l_simAXIMem.io_axi4.elements.head._2 :<>= soc.memory.viewAs[AXI4Bundle].waiveAll
51
52 soc.io.clock := clock.asBool
53 soc.io.reset := (reset.asBool || soc.io.debug_reset).asAsyncReset
54 soc.io.extIntrs := simMMIO.io.interrupt.intrVec
55 soc.io.sram_config := 0.U
56 soc.io.pll0_lock := true.B
57 soc.io.cacheable_check := DontCare
58 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U)

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55 soc.io.clock := clock.asBool
56 soc.io.reset := (reset.asBool || soc.io.debug_reset).asAsyncReset
57 soc.io.extIntrs := simMMIO.io.interrupt.intrVec
58 soc.io.sram_config := 0.U
59 soc.io.pll0_lock := true.B
60 soc.io.cacheable_check := DontCare
61 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U)

--- 60 unchanged lines hidden ---