SC.scala (8b33cd30e0034914b58520e0dc3c0c4b1aad6a03) SC.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 19 unchanged lines hidden (view full) ---

28package xiangshan.frontend
29
30import chisel3._
31import chisel3.util._
32import org.chipsalliance.cde.config.Parameters
33import scala.{Tuple2 => &}
34import scala.math.min
35import utility._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 19 unchanged lines hidden (view full) ---

28package xiangshan.frontend
29
30import chisel3._
31import chisel3.util._
32import org.chipsalliance.cde.config.Parameters
33import scala.{Tuple2 => &}
34import scala.math.min
35import utility._
36import utility.mbist.MbistPipeline
36import xiangshan._
37
38trait HasSCParameter extends TageParams {}
39
40class SCReq(implicit p: Parameters) extends TageReq
41
42abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}
43abstract class SCModule(implicit p: Parameters) extends TageModule with HasSCParameter {}

--- 31 unchanged lines hidden (view full) ---

75 val table = Module(new SRAMTemplate(
76 SInt(ctrBits.W),
77 set = nRows,
78 way = 2 * TageBanks,
79 shouldReset = true,
80 holdRead = true,
81 singlePort = false,
82 bypassWrite = true,
37import xiangshan._
38
39trait HasSCParameter extends TageParams {}
40
41class SCReq(implicit p: Parameters) extends TageReq
42
43abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}
44abstract class SCModule(implicit p: Parameters) extends TageModule with HasSCParameter {}

--- 31 unchanged lines hidden (view full) ---

76 val table = Module(new SRAMTemplate(
77 SInt(ctrBits.W),
78 set = nRows,
79 way = 2 * TageBanks,
80 shouldReset = true,
81 holdRead = true,
82 singlePort = false,
83 bypassWrite = true,
83 withClockGate = true
84 withClockGate = true,
85 hasMbist = hasMbist
84 ))
86 ))
85
87 private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeSc", hasMbist)
86 // def getIdx(hist: UInt, pc: UInt) = {
87 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
88 // }
89
90 val idxFhInfo = (histLen, min(log2Ceil(nRows), histLen))
91
92 def getFoldedHistoryInfo = Set(idxFhInfo).filter(_._1 > 0)
93

--- 381 unchanged lines hidden --- 		88 // def getIdx(hist: UInt, pc: UInt) = {
89 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
90 // }
91
92 val idxFhInfo = (histLen, min(log2Ceil(nRows), histLen))
93
94 def getFoldedHistoryInfo = Set(idxFhInfo).filter(_._1 > 0)
95

--- 381 unchanged lines hidden ---