NewFtq.scala (d33d62c44aa38d82d5df728df309af895734f3e7) NewFtq.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24
25package xiangshan.frontend
26
27import chisel3._
28import chisel3.util._
29import org.chipsalliance.cde.config.Parameters
30import utility._
31import utility.ChiselDB
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24
25package xiangshan.frontend
26
27import chisel3._
28import chisel3.util._
29import org.chipsalliance.cde.config.Parameters
30import utility._
31import utility.ChiselDB
32import utility.mbist.MbistPipeline
32import utils._
33import xiangshan._
34import xiangshan.backend.CtrlToFtqIO
33import utils._
34import xiangshan._
35import xiangshan.backend.CtrlToFtqIO
35import xiangshan.backend.decode.ImmUnion
36import xiangshan.frontend.icache._
37
38class FtqDebugBundle extends Bundle {
39 val pc = UInt(39.W)
40 val target = UInt(39.W)
41 val isBr = Bool()
42 val isJmp = Bool()
43 val isCall = Bool()

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71 val ren = Input(Vec(numRead, Bool()))
72 val rdata = Output(Vec(numRead, gen))
73 val waddr = Input(UInt(log2Up(FtqSize).W))
74 val wen = Input(Bool())
75 val wdata = Input(gen)
76 })
77
78 for (i <- 0 until numRead) {
36import xiangshan.frontend.icache._
37
38class FtqDebugBundle extends Bundle {
39 val pc = UInt(39.W)
40 val target = UInt(39.W)
41 val isBr = Bool()
42 val isJmp = Bool()
43 val isCall = Bool()

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71 val ren = Input(Vec(numRead, Bool()))
72 val rdata = Output(Vec(numRead, gen))
73 val waddr = Input(UInt(log2Up(FtqSize).W))
74 val wen = Input(Bool())
75 val wdata = Input(gen)
76 })
77
78 for (i <- 0 until numRead) {
79 val sram = Module(new SRAMTemplate(gen, FtqSize, withClockGate = true))
79 val sram = Module(new SRAMTemplate(gen, FtqSize, withClockGate = true, hasMbist = hasMbist))
80 sram.io.r.req.valid := io.ren(i)
81 sram.io.r.req.bits.setIdx := io.raddr(i)
82 io.rdata(i) := sram.io.r.resp.data(0)
83 sram.io.w.req.valid := io.wen
84 sram.io.w.req.bits.setIdx := io.waddr
85 sram.io.w.req.bits.data := VecInit(io.wdata)
86 }
87

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654 FtqSize,
655 IfuRedirectNum + FtqRedirectAheadNum,
656 1,
657 hasRen = true
658 ))
659 ftb_entry_mem.io.wen(0) := io.fromBpu.resp.bits.lastStage.valid(3)
660 ftb_entry_mem.io.waddr(0) := io.fromBpu.resp.bits.lastStage.ftq_idx.value
661 ftb_entry_mem.io.wdata(0) := io.fromBpu.resp.bits.last_stage_ftb_entry
80 sram.io.r.req.valid := io.ren(i)
81 sram.io.r.req.bits.setIdx := io.raddr(i)
82 io.rdata(i) := sram.io.r.resp.data(0)
83 sram.io.w.req.valid := io.wen
84 sram.io.w.req.bits.setIdx := io.waddr
85 sram.io.w.req.bits.data := VecInit(io.wdata)
86 }
87

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654 FtqSize,
655 IfuRedirectNum + FtqRedirectAheadNum,
656 1,
657 hasRen = true
658 ))
659 ftb_entry_mem.io.wen(0) := io.fromBpu.resp.bits.lastStage.valid(3)
660 ftb_entry_mem.io.waddr(0) := io.fromBpu.resp.bits.lastStage.ftq_idx.value
661 ftb_entry_mem.io.wdata(0) := io.fromBpu.resp.bits.last_stage_ftb_entry
662 private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeFtq", hasMbist)
662
663 // multi-write
664 val update_target = Reg(Vec(FtqSize, UInt(VAddrBits.W))) // could be taken target or fallThrough //TODO: remove this
665 val newest_entry_target = Reg(UInt(VAddrBits.W))
666 val newest_entry_target_modified = RegInit(false.B)
667 val newest_entry_ptr = Reg(new FtqPtr)
668 val newest_entry_ptr_modified = RegInit(false.B)
669 val cfiIndex_vec = Reg(Vec(FtqSize, ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))))

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664 // multi-write
665 val update_target = Reg(Vec(FtqSize, UInt(VAddrBits.W))) // could be taken target or fallThrough //TODO: remove this
666 val newest_entry_target = Reg(UInt(VAddrBits.W))
667 val newest_entry_target_modified = RegInit(false.B)
668 val newest_entry_ptr = Reg(new FtqPtr)
669 val newest_entry_ptr_modified = RegInit(false.B)
670 val cfiIndex_vec = Reg(Vec(FtqSize, ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))))

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