FTB.scala (03426fe221938ab0f0d83457b4c77734b35fdc71) FTB.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package xiangshan.frontend
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import scala.{Tuple2 => &}
23import utility._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package xiangshan.frontend
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import scala.{Tuple2 => &}
23import utility._
24import utility.mbist.MbistPipeline
24import xiangshan._
25
26trait FTBParams extends HasXSParameter with HasBPUConst {
27 val numEntries = FtbSize
28 val numWays = FtbWays
29 val numSets = numEntries / numWays // 512
30 val tagLength = FtbTagLength
31

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493 // Extract holdRead logic to fix bug that update read override predict read result
494 val ftb = Module(new SRAMTemplate(
495 new FTBEntryWithTag,
496 set = numSets,
497 way = numWays,
498 shouldReset = true,
499 holdRead = false,
500 singlePort = true,
25import xiangshan._
26
27trait FTBParams extends HasXSParameter with HasBPUConst {
28 val numEntries = FtbSize
29 val numWays = FtbWays
30 val numSets = numEntries / numWays // 512
31 val tagLength = FtbTagLength
32

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494 // Extract holdRead logic to fix bug that update read override predict read result
495 val ftb = Module(new SRAMTemplate(
496 new FTBEntryWithTag,
497 set = numSets,
498 way = numWays,
499 shouldReset = true,
500 holdRead = false,
501 singlePort = true,
501 withClockGate = true
502 withClockGate = true,
503 hasMbist = hasMbist
502 ))
504 ))
503 val ftb_r_entries = ftb.io.r.resp.data.map(_.entry)
505 private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeFtb", hasMbist)
506 val ftb_r_entries = ftb.io.r.resp.data.map(_.entry)
504
505 val pred_rdata = HoldUnless(
506 ftb.io.r.resp.data,
507 RegNext(io.req_pc.valid && !io.update_access),
508 init = Some(VecInit.fill(numWays)(0.U.asTypeOf(new FTBEntryWithTag)))
509 ) // rdata has ftb_entry.valid, shoud reset
510 ftb.io.r.req.valid := io.req_pc.valid || io.u_req_pc.valid // io.s0_fire
511 ftb.io.r.req.bits.setIdx := Mux(

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508 val pred_rdata = HoldUnless(
509 ftb.io.r.resp.data,
510 RegNext(io.req_pc.valid && !io.update_access),
511 init = Some(VecInit.fill(numWays)(0.U.asTypeOf(new FTBEntryWithTag)))
512 ) // rdata has ftb_entry.valid, shoud reset
513 ftb.io.r.req.valid := io.req_pc.valid || io.u_req_pc.valid // io.s0_fire
514 ftb.io.r.req.bits.setIdx := Mux(

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