BPU.scala (c5e28a9a871afdf94bb2dd0a343a6f58d9c0e8a5) BPU.scala (50f995b131e7447267057b9b1459700a4f4a0823)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 422 unchanged lines hidden (view full) ---

431 foldedGhGen.register(s1_valid, s1_predicted_fh, Some("s1_FGH"), 4)
432 ghistPtrGen.register(s1_valid, s1_predicted_ghist_ptr, Some("s1_GHPtr"), 4)
433 lastBrNumOHGen.register(s1_valid, resp.s1.lastBrPosOH.asUInt, Some("s1_BrNumOH"), 4)
434 aheadFhObGen.register(s1_valid, s1_ahead_fh_ob_src, Some("s1_AFHOB"), 4)
435 ghvBitWriteGens.zip(s1_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
436 b.register(w.reduce(_||_), s1_ghv_wdatas(i), Some(s"s1_new_bit_$i"), 4)
437 }
438
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 422 unchanged lines hidden (view full) ---

431 foldedGhGen.register(s1_valid, s1_predicted_fh, Some("s1_FGH"), 4)
432 ghistPtrGen.register(s1_valid, s1_predicted_ghist_ptr, Some("s1_GHPtr"), 4)
433 lastBrNumOHGen.register(s1_valid, resp.s1.lastBrPosOH.asUInt, Some("s1_BrNumOH"), 4)
434 aheadFhObGen.register(s1_valid, s1_ahead_fh_ob_src, Some("s1_AFHOB"), 4)
435 ghvBitWriteGens.zip(s1_ghv_wens).zipWithIndex.map{case ((b, w), i) =>
436 b.register(w.reduce(_||_), s1_ghv_wdatas(i), Some(s"s1_new_bit_$i"), 4)
437 }
438
439 def preds_needs_redirect_vec(x: BranchPredictionBundle, y: BranchPredictionBundle) = {
439 class PreviousPredInfo extends Bundle {
440 val target = UInt(VAddrBits.W)
441 val lastBrPosOH = UInt((numBr+1).W)
442 val taken = Bool()
443 val cfiIndex = UInt(log2Ceil(PredictWidth).W)
444 }
445
446 def preds_needs_redirect_vec(x: PreviousPredInfo, y: BranchPredictionBundle) = {
440 VecInit(
447 VecInit(
441 x.getTarget =/= y.getTarget,
442 x.lastBrPosOH.asUInt =/= y.lastBrPosOH.asUInt,
448 x.target =/= y.getTarget,
449 x.lastBrPosOH =/= y.lastBrPosOH.asUInt,
443 x.taken =/= y.taken,
450 x.taken =/= y.taken,
444 (x.taken && y.taken) && x.cfiIndex.bits =/= y.cfiIndex.bits,
451 (x.taken && y.taken) && x.cfiIndex =/= y.cfiIndex.bits,
445 // x.shouldShiftVec.asUInt =/= y.shouldShiftVec.asUInt,
446 // x.brTaken =/= y.brTaken
447 )
448 }
449
450 // s2
451 val s2_possible_predicted_ghist_ptrs = (0 to numBr).map(s2_ghist_ptr - _.U)
452 val s2_predicted_ghist_ptr = Mux1H(resp.s2.lastBrPosOH, s2_possible_predicted_ghist_ptrs)

--- 23 unchanged lines hidden (view full) ---

476 Mux1H(
477 (0 until numBr).map(b => (
478 (s2_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s2.shouldShiftVec(b),
479 resp.s2.full_pred.real_br_taken_mask()(b)
480 ))
481 )
482 )
483
452 // x.shouldShiftVec.asUInt =/= y.shouldShiftVec.asUInt,
453 // x.brTaken =/= y.brTaken
454 )
455 }
456
457 // s2
458 val s2_possible_predicted_ghist_ptrs = (0 to numBr).map(s2_ghist_ptr - _.U)
459 val s2_predicted_ghist_ptr = Mux1H(resp.s2.lastBrPosOH, s2_possible_predicted_ghist_ptrs)

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483 Mux1H(
484 (0 until numBr).map(b => (
485 (s2_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s2.shouldShiftVec(b),
486 resp.s2.full_pred.real_br_taken_mask()(b)
487 ))
488 )
489 )
490
484 val previous_s1_pred = RegEnable(resp.s1, 0.U.asTypeOf(resp.s1), s1_fire)
491 val s1_pred_info = Wire(new PreviousPredInfo)
492 s1_pred_info.target := resp.s1.getTarget
493 s1_pred_info.lastBrPosOH := resp.s1.lastBrPosOH.asUInt
494 s1_pred_info.taken := resp.s1.taken
495 s1_pred_info.cfiIndex := resp.s1.cfiIndex.bits
485
496
486 val s2_redirect_s1_last_pred_vec = preds_needs_redirect_vec(previous_s1_pred, resp.s2)
497 val previous_s1_pred_info = RegEnable(s1_pred_info, init=0.U.asTypeOf(s1_pred_info), s1_fire)
487
498
499 val s2_redirect_s1_last_pred_vec = preds_needs_redirect_vec(previous_s1_pred_info, resp.s2)
500
488 s2_redirect := s2_fire && s2_redirect_s1_last_pred_vec.reduce(_||_)
489
490 npcGen.register(s2_redirect, resp.s2.getTarget, Some("s2_target"), 5)
491 foldedGhGen.register(s2_redirect, s2_predicted_fh, Some("s2_FGH"), 5)
492 ghistPtrGen.register(s2_redirect, s2_predicted_ghist_ptr, Some("s2_GHPtr"), 5)
493 lastBrNumOHGen.register(s2_redirect, resp.s2.lastBrPosOH.asUInt, Some("s2_BrNumOH"), 5)
494 aheadFhObGen.register(s2_redirect, s2_ahead_fh_ob_src, Some("s2_AFHOB"), 5)
495 ghvBitWriteGens.zip(s2_ghv_wens).zipWithIndex.map{case ((b, w), i) =>

--- 210 unchanged lines hidden --- 		501 s2_redirect := s2_fire && s2_redirect_s1_last_pred_vec.reduce(_||_)
502
503 npcGen.register(s2_redirect, resp.s2.getTarget, Some("s2_target"), 5)
504 foldedGhGen.register(s2_redirect, s2_predicted_fh, Some("s2_FGH"), 5)
505 ghistPtrGen.register(s2_redirect, s2_predicted_ghist_ptr, Some("s2_GHPtr"), 5)
506 lastBrNumOHGen.register(s2_redirect, resp.s2.lastBrPosOH.asUInt, Some("s2_BrNumOH"), 5)
507 aheadFhObGen.register(s2_redirect, s2_ahead_fh_ob_src, Some("s2_AFHOB"), 5)
508 ghvBitWriteGens.zip(s2_ghv_wens).zipWithIndex.map{case ((b, w), i) =>

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