WPU.scala (0466583513e4c1ddbbb566b866b8963635acb20f) WPU.scala (8891a219bbc84f568e1d134854d8d5ed86d6d560)
1package xiangshan.cache.wpu
2
1package xiangshan.cache.wpu
2
3import chipsalliance.rocketchip.config.{Field, Parameters}
3import org.chipsalliance.cde.config.{Field, Parameters}
4import chisel3._
5import chisel3.util._
6import utils.XSPerfAccumulate
7import xiangshan.cache.{HasL1CacheParameters, L1CacheParameters}
8import xiangshan.{XSBundle, XSModule}
9
10/*
11// TODO: need to learn the specific grammar

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149
150 def get_hash_utag(addr: UInt): UInt = {
151 val utagQuotient = vtagBits / utagBits
152 val utagRemainder = vtagBits % utagBits
153 val vtag = get_vir_tag(addr)
154
155 /* old */
156 vtag(utagBits * 2 - 1, utagBits) ^ vtag(utagBits - 1, 0)
4import chisel3._
5import chisel3.util._
6import utils.XSPerfAccumulate
7import xiangshan.cache.{HasL1CacheParameters, L1CacheParameters}
8import xiangshan.{XSBundle, XSModule}
9
10/*
11// TODO: need to learn the specific grammar

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149
150 def get_hash_utag(addr: UInt): UInt = {
151 val utagQuotient = vtagBits / utagBits
152 val utagRemainder = vtagBits % utagBits
153 val vtag = get_vir_tag(addr)
154
155 /* old */
156 vtag(utagBits * 2 - 1, utagBits) ^ vtag(utagBits - 1, 0)
157
157
158 /* new */
159 // val tmp = vtag(utagQuotient * utagBits - 1, 0).asTypeOf(Vec(utagQuotient, UInt(utagBits.W)))
160 // val res1 = tmp.reduce(_ ^ _)
161 // val res2 = Wire(UInt(utagRemainder.W))
162 // if(utagRemainder!=0){
163 // res2 := res1(utagRemainder - 1, 0) ^ vtag(vtagBits - 1, utagBits * utagQuotient)
164 // Cat(res1(utagBits - 1, utagRemainder), res2)
165 // }else{

--- 66 unchanged lines hidden --- 		158 /* new */
159 // val tmp = vtag(utagQuotient * utagBits - 1, 0).asTypeOf(Vec(utagQuotient, UInt(utagBits.W)))
160 // val res1 = tmp.reduce(_ ^ _)
161 // val res2 = Wire(UInt(utagRemainder.W))
162 // if(utagRemainder!=0){
163 // res2 := res1(utagRemainder - 1, 0) ^ vtag(vtagBits - 1, utagBits * utagQuotient)
164 // Cat(res1(utagBits - 1, utagRemainder), res2)
165 // }else{

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