TLB.scala (57fe673e233797f17bc9643606a8fffed9228266) TLB.scala (7d45a146d3c44839ba821bb91ca4950dc2b817f2)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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314 for (i <- ptw.req.indices) {
315 XSDebug(ptw.req(i).fire(), p"L2TLB req:${ptw.req(i).bits}\n")
316 }
317 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n")
318
319 println(s"${q.name}: normal page: ${q.normalNWays} ${q.normalAssociative} ${q.normalReplacer.get} super page: ${q.superNWays} ${q.superAssociative} ${q.superReplacer.get}")
320
321 if (env.EnableDifftest) {
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 305 unchanged lines hidden (view full) ---

314 for (i <- ptw.req.indices) {
315 XSDebug(ptw.req(i).fire(), p"L2TLB req:${ptw.req(i).bits}\n")
316 }
317 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n")
318
319 println(s"${q.name}: normal page: ${q.normalNWays} ${q.normalAssociative} ${q.normalReplacer.get} super page: ${q.superNWays} ${q.superAssociative} ${q.superReplacer.get}")
320
321 if (env.EnableDifftest) {
322 val l1tlbid = Wire(UInt(2.W))
323 if (q.name == "itlb") {
324 l1tlbid := 0.U
325 } else if (q.name == "ldtlb") {
326 l1tlbid := 1.U
327 } else if (q.name == "sttlb") {
328 l1tlbid := 2.U
329 } else {
330 l1tlbid := 3.U
331 }
332
333 for (i <- 0 until Width) {
334 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld
335 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld
322 for (i <- 0 until Width) {
323 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld
324 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld
336 val difftest = Module(new DifftestL1TLBEvent)
337 difftest.io.clock := clock
338 difftest.io.coreid := p(XSCoreParamsKey).HartId.asUInt
339 difftest.io.valid := l1tlbid =/= 3.U && RegNext(io.requestor(i).req.fire) && !RegNext(io.requestor(i).req_kill) && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && portTranslateEnable(i)
340 difftest.io.index := i.U
341 difftest.io.l1tlbid := l1tlbid
342 difftest.io.satp := io.csr.satp.ppn
343 difftest.io.vpn := RegNext(get_pn(req_in(i).bits.vaddr))
344 difftest.io.ppn := get_pn(io.requestor(i).resp.bits.paddr(0))
325 val difftest = DifftestModule(new DiffL1TLBEvent)
326 difftest.clock := clock
327 difftest.coreid := p(XSCoreParamsKey).HartId.asUInt
328 difftest.valid := RegNext(io.requestor(i).req.fire) && !RegNext(io.requestor(i).req_kill) && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && portTranslateEnable(i)
329 if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) {
330 difftest.valid := false.B
331 }
332 difftest.index := TLBDiffId(p(XSCoreParamsKey).HartId).U
333 difftest.satp := io.csr.satp.ppn
334 difftest.vpn := RegNext(get_pn(req_in(i).bits.vaddr))
335 difftest.ppn := get_pn(io.requestor(i).resp.bits.paddr(0))
345 }
346 }
336 }
337 }
338}
347
339
340object TLBDiffId {
341 var i: Int = 0
342 var lastHartId: Int = -1
343 def apply(hartId: Int): Int = {
344 if (lastHartId != hartId) {
345 i = 0
346 lastHartId = hartId
347 }
348 i += 1
349 i - 1
350 }
348}
349
350class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q)
351class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q)
352
353class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule {
354 val io = IO(new TlbReplaceIO(Width, q))
355

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352
353class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q)
354class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q)
355
356class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule {
357 val io = IO(new TlbReplaceIO(Width, q))
358

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