Rob.scala (ffebba96012c2d9027811c03f1b0bfa91aa6b6fc) Rob.scala (c0f8424bf94d8e6b9c520cebd68c2a0de3d4675c)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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112 val bankNum = 8
113 assert(RobSize % bankNum == 0, "RobSize % bankNum must be 0")
114 val robEntries = Reg(Vec(RobSize, new RobEntryBundle))
115 // pointers
116 // For enqueue ptr, we don't duplicate it since only enqueue needs it.
117 val enqPtrVec = Wire(Vec(RenameWidth, new RobPtr))
118 val deqPtrVec = Wire(Vec(CommitWidth, new RobPtr))
119 val walkPtrVec = Reg(Vec(CommitWidth, new RobPtr))
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 103 unchanged lines hidden (view full) ---

112 val bankNum = 8
113 assert(RobSize % bankNum == 0, "RobSize % bankNum must be 0")
114 val robEntries = Reg(Vec(RobSize, new RobEntryBundle))
115 // pointers
116 // For enqueue ptr, we don't duplicate it since only enqueue needs it.
117 val enqPtrVec = Wire(Vec(RenameWidth, new RobPtr))
118 val deqPtrVec = Wire(Vec(CommitWidth, new RobPtr))
119 val walkPtrVec = Reg(Vec(CommitWidth, new RobPtr))
120 val walkPtrTrue = Reg(new RobPtr)
120 val lastWalkPtr = Reg(new RobPtr)
121 val allowEnqueue = RegInit(true.B)
122
123 /**
124 * Enqueue (from dispatch)
125 */
126 // special cases
127 val hasBlockBackward = RegInit(false.B)

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535 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
536 }.elsewhen(RegNext(io.redirect.valid)){
537 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
538 }.elsewhen(state === s_walk){
539 shouldWalkVec := VecInit(walkingPtrVec.map(_ <= lastWalkPtr).zip(donotNeedWalk).map(x => x._1 && !x._2))
540 }.otherwise(
541 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
542 )
121 val lastWalkPtr = Reg(new RobPtr)
122 val allowEnqueue = RegInit(true.B)
123
124 /**
125 * Enqueue (from dispatch)
126 */
127 // special cases
128 val hasBlockBackward = RegInit(false.B)

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536 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
537 }.elsewhen(RegNext(io.redirect.valid)){
538 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
539 }.elsewhen(state === s_walk){
540 shouldWalkVec := VecInit(walkingPtrVec.map(_ <= lastWalkPtr).zip(donotNeedWalk).map(x => x._1 && !x._2))
541 }.otherwise(
542 shouldWalkVec := 0.U.asTypeOf(shouldWalkVec)
543 )
543 val walkFinished = walkPtrVec.head > lastWalkPtr
544 val walkFinished = walkPtrTrue > lastWalkPtr
544 rab.io.fromRob.walkEnd := state === s_walk && walkFinished
545 vtypeBuffer.io.fromRob.walkEnd := state === s_walk && walkFinished
546
547 require(RenameWidth <= CommitWidth)
548
549 // wiring to csr
550 val (wflags, dirtyFs) = (0 until CommitWidth).map(i => {
551 val v = io.commits.commitValid(i)

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696
697 // next walkPtrVec:
698 // (1) redirect occurs: update according to state
699 // (2) walk: move forwards
700 val deqPtrReadBank = deqPtrVec_next(0).lineHeadPtr
701 val deqPtrVecForWalk = VecInit((0 until CommitWidth).map(i => deqPtrReadBank + i.U))
702 val snapPtrReadBank = snapshots(io.snpt.snptSelect)(0).lineHeadPtr
703 val snapPtrVecForWalk = VecInit((0 until CommitWidth).map(i => snapPtrReadBank + i.U))
545 rab.io.fromRob.walkEnd := state === s_walk && walkFinished
546 vtypeBuffer.io.fromRob.walkEnd := state === s_walk && walkFinished
547
548 require(RenameWidth <= CommitWidth)
549
550 // wiring to csr
551 val (wflags, dirtyFs) = (0 until CommitWidth).map(i => {
552 val v = io.commits.commitValid(i)

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697
698 // next walkPtrVec:
699 // (1) redirect occurs: update according to state
700 // (2) walk: move forwards
701 val deqPtrReadBank = deqPtrVec_next(0).lineHeadPtr
702 val deqPtrVecForWalk = VecInit((0 until CommitWidth).map(i => deqPtrReadBank + i.U))
703 val snapPtrReadBank = snapshots(io.snpt.snptSelect)(0).lineHeadPtr
704 val snapPtrVecForWalk = VecInit((0 until CommitWidth).map(i => snapPtrReadBank + i.U))
704 val walkPtrVec_next = Mux(io.redirect.valid,
705 val walkPtrVec_next: Vec[RobPtr] = Mux(io.redirect.valid,
705 Mux(io.snpt.useSnpt, snapPtrVecForWalk, deqPtrVecForWalk),
706 Mux((state === s_walk) && !walkFinished, VecInit(walkPtrVec.map(_ + CommitWidth.U)), walkPtrVec)
707 )
706 Mux(io.snpt.useSnpt, snapPtrVecForWalk, deqPtrVecForWalk),
707 Mux((state === s_walk) && !walkFinished, VecInit(walkPtrVec.map(_ + CommitWidth.U)), walkPtrVec)
708 )
709 val walkPtrTrue_next: RobPtr = Mux(io.redirect.valid,
710 Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0), deqPtrVec_next(0)),
711 Mux((state === s_walk) && !walkFinished, walkPtrVec_next.head, walkPtrTrue)
712 )
708 walkPtrHead := walkPtrVec_next.head
709 walkPtrVec := walkPtrVec_next
713 walkPtrHead := walkPtrVec_next.head
714 walkPtrVec := walkPtrVec_next
715 walkPtrTrue := walkPtrTrue_next
710 // T io.redirect.valid, T+1 walkPtrLowBits update, T+2 donotNeedWalk update
711 val walkPtrLowBits = Reg(UInt(bankAddrWidth.W))
712 when(io.redirect.valid){
713 walkPtrLowBits := Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0).value(bankAddrWidth-1, 0), deqPtrVec_next(0).value(bankAddrWidth-1, 0))
714 }
715 when(io.redirect.valid) {
716 donotNeedWalk := Fill(donotNeedWalk.length, true.B).asTypeOf(donotNeedWalk)
717 }.elsewhen(RegNext(io.redirect.valid)){
718 donotNeedWalk := (0 until CommitWidth).map(i => (i.U < walkPtrLowBits))
716 // T io.redirect.valid, T+1 walkPtrLowBits update, T+2 donotNeedWalk update
717 val walkPtrLowBits = Reg(UInt(bankAddrWidth.W))
718 when(io.redirect.valid){
719 walkPtrLowBits := Mux(io.snpt.useSnpt, snapshots(io.snpt.snptSelect)(0).value(bankAddrWidth-1, 0), deqPtrVec_next(0).value(bankAddrWidth-1, 0))
720 }
721 when(io.redirect.valid) {
722 donotNeedWalk := Fill(donotNeedWalk.length, true.B).asTypeOf(donotNeedWalk)
723 }.elsewhen(RegNext(io.redirect.valid)){
724 donotNeedWalk := (0 until CommitWidth).map(i => (i.U < walkPtrLowBits))
719 }.otherwise(
725 }.otherwise{
720 donotNeedWalk := 0.U.asTypeOf(donotNeedWalk)
726 donotNeedWalk := 0.U.asTypeOf(donotNeedWalk)
721 )
727 }
722 walkDestSizeDeqGroup.zip(walkPtrVec_next).map {
723 case (reg, ptrNext) => reg := robEntries(deqPtr.value).realDestSize
724 }
725 val numValidEntries = distanceBetween(enqPtr, deqPtr)
726 val commitCnt = PopCount(io.commits.commitValid)
727
728 allowEnqueue := numValidEntries + dispatchNum <= (RobSize - CommitWidth).U
729

--- 647 unchanged lines hidden --- 		728 walkDestSizeDeqGroup.zip(walkPtrVec_next).map {
729 case (reg, ptrNext) => reg := robEntries(deqPtr.value).realDestSize
730 }
731 val numValidEntries = distanceBetween(enqPtr, deqPtr)
732 val commitCnt = PopCount(io.commits.commitValid)
733
734 allowEnqueue := numValidEntries + dispatchNum <= (RobSize - CommitWidth).U
735

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