Rob.scala (db0002463cde5824cd40d03b15a00b3d933b9133) Rob.scala (bd5909d0fbe65a8baf96c66f093f9e3cbde8b75e)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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52 val io = IO(new Bundle() {
53 val hartId = Input(UInt(hartIdLen.W))
54 val redirect = Input(Valid(new Redirect))
55 val enq = new RobEnqIO
56 val flushOut = ValidIO(new Redirect)
57 val exception = ValidIO(new ExceptionInfo)
58 // exu + brq
59 val writeback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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52 val io = IO(new Bundle() {
53 val hartId = Input(UInt(hartIdLen.W))
54 val redirect = Input(Valid(new Redirect))
55 val enq = new RobEnqIO
56 val flushOut = ValidIO(new Redirect)
57 val exception = ValidIO(new ExceptionInfo)
58 // exu + brq
59 val writeback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
60 val exuWriteback: MixedVec[ValidIO[ExuOutput]] = Flipped(params.genWrite2CtrlBundles)
60 val writebackNums = Flipped(Vec(writeback.size - params.StdCnt, ValidIO(UInt(writeback.size.U.getWidth.W))))
61 val writebackNeedFlush = Input(Vec(params.allExuParams.filter(_.needExceptionGen).length, Bool()))
62 val commits = Output(new RobCommitIO)
63 val rabCommits = Output(new RabCommitIO)
64 val diffCommits = if (backendParams.debugEn) Some(Output(new DiffCommitIO)) else None
65 val isVsetFlushPipe = Output(Bool())
66 val lsq = new RobLsqIO
67 val robDeqPtr = Output(new RobPtr)

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94 val debugTopDown = new Bundle {
95 val toCore = new RobCoreTopDownIO
96 val toDispatch = new RobDispatchTopDownIO
97 val robHeadLqIdx = Valid(new LqPtr)
98 }
99 val debugRolling = new RobDebugRollingIO
100 })
101
61 val writebackNums = Flipped(Vec(writeback.size - params.StdCnt, ValidIO(UInt(writeback.size.U.getWidth.W))))
62 val writebackNeedFlush = Input(Vec(params.allExuParams.filter(_.needExceptionGen).length, Bool()))
63 val commits = Output(new RobCommitIO)
64 val rabCommits = Output(new RabCommitIO)
65 val diffCommits = if (backendParams.debugEn) Some(Output(new DiffCommitIO)) else None
66 val isVsetFlushPipe = Output(Bool())
67 val lsq = new RobLsqIO
68 val robDeqPtr = Output(new RobPtr)

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95 val debugTopDown = new Bundle {
96 val toCore = new RobCoreTopDownIO
97 val toDispatch = new RobDispatchTopDownIO
98 val robHeadLqIdx = Valid(new LqPtr)
99 }
100 val debugRolling = new RobDebugRollingIO
101 })
102
102 val exuWBs: Seq[ValidIO[ExuOutput]] = io.writeback.filter(!_.bits.params.hasStdFu).toSeq
103 val stdWBs: Seq[ValidIO[ExuOutput]] = io.writeback.filter(_.bits.params.hasStdFu).toSeq
104 val fflagsWBs = io.writeback.filter(x => x.bits.fflags.nonEmpty).toSeq
103 val exuWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(!_.bits.params.hasStdFu).toSeq
104 val stdWBs: Seq[ValidIO[ExuOutput]] = io.exuWriteback.filter(_.bits.params.hasStdFu).toSeq
105 val fflagsWBs = io.exuWriteback.filter(x => x.bits.fflags.nonEmpty).toSeq
105 val exceptionWBs = io.writeback.filter(x => x.bits.exceptionVec.nonEmpty).toSeq
106 val redirectWBs = io.writeback.filter(x => x.bits.redirect.nonEmpty).toSeq
106 val exceptionWBs = io.writeback.filter(x => x.bits.exceptionVec.nonEmpty).toSeq
107 val redirectWBs = io.writeback.filter(x => x.bits.redirect.nonEmpty).toSeq
107 val vxsatWBs = io.writeback.filter(x => x.bits.vxsat.nonEmpty).toSeq
108 val vxsatWBs = io.exuWriteback.filter(x => x.bits.vxsat.nonEmpty).toSeq
108
109 val numExuWbPorts = exuWBs.length
110 val numStdWbPorts = stdWBs.length
111 val bankAddrWidth = log2Up(CommitWidth)
112
113 println(s"Rob: size $RobSize, numExuWbPorts: $numExuWbPorts, numStdWbPorts: $numStdWbPorts, commitwidth: $CommitWidth")
114
115 val rab = Module(new RenameBuffer(RabSize))

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110 val numExuWbPorts = exuWBs.length
111 val numStdWbPorts = stdWBs.length
112 val bankAddrWidth = log2Up(CommitWidth)
113
114 println(s"Rob: size $RobSize, numExuWbPorts: $numExuWbPorts, numStdWbPorts: $numStdWbPorts, commitwidth: $CommitWidth")
115
116 val rab = Module(new RenameBuffer(RabSize))

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