Rob.scala (9b9e991b39279f1a5b08138e808acbef33217da6) Rob.scala (6810d1e8e7c0789e9f50ee6bdd52010b8ce506ef)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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326 lazy val module = new RobImp(this)(p, params)
327}
328
329class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper)
330 with HasXSParameter with HasCircularQueuePtrHelper with HasPerfEvents {
331
332 private val LduCnt = params.LduCnt
333 private val StaCnt = params.StaCnt
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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326 lazy val module = new RobImp(this)(p, params)
327}
328
329class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper)
330 with HasXSParameter with HasCircularQueuePtrHelper with HasPerfEvents {
331
332 private val LduCnt = params.LduCnt
333 private val StaCnt = params.StaCnt
334 private val HyuCnt = params.HyuCnt
334
335 val io = IO(new Bundle() {
336 val hartId = Input(UInt(8.W))
337 val redirect = Input(Valid(new Redirect))
338 val enq = new RobEnqIO
339 val flushOut = ValidIO(new Redirect)
340 val exception = ValidIO(new ExceptionInfo)
341 // exu + brq

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353 val headNotReady = Output(Bool())
354 val cpu_halt = Output(Bool())
355 val wfi_enable = Input(Bool())
356
357 val debug_ls = Flipped(new DebugLSIO)
358 val debugRobHead = Output(new DynInst)
359 val debugEnqLsq = Input(new LsqEnqIO)
360 val debugHeadLsIssue = Input(Bool())
335
336 val io = IO(new Bundle() {
337 val hartId = Input(UInt(8.W))
338 val redirect = Input(Valid(new Redirect))
339 val enq = new RobEnqIO
340 val flushOut = ValidIO(new Redirect)
341 val exception = ValidIO(new ExceptionInfo)
342 // exu + brq

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354 val headNotReady = Output(Bool())
355 val cpu_halt = Output(Bool())
356 val wfi_enable = Input(Bool())
357
358 val debug_ls = Flipped(new DebugLSIO)
359 val debugRobHead = Output(new DynInst)
360 val debugEnqLsq = Input(new LsqEnqIO)
361 val debugHeadLsIssue = Input(Bool())
361 val lsTopdownInfo = Vec(LduCnt, Input(new LsTopdownInfo))
362 val lsTopdownInfo = Vec(LduCnt + HyuCnt, Input(new LsTopdownInfo))
362 val debugTopDown = new Bundle {
363 val toCore = new RobCoreTopDownIO
364 val toDispatch = new RobDispatchTopDownIO
365 val robHeadLqIdx = Valid(new LqPtr)
366 }
367 val debugRolling = new RobDebugRollingIO
368 })
369

--- 1062 unchanged lines hidden --- 		363 val debugTopDown = new Bundle {
364 val toCore = new RobCoreTopDownIO
365 val toDispatch = new RobDispatchTopDownIO
366 val robHeadLqIdx = Valid(new LqPtr)
367 }
368 val debugRolling = new RobDebugRollingIO
369 })
370

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