Rob.scala (0d32f7132f120ac0b32ab552fe0da4934208dd01) Rob.scala (7d45a146d3c44839ba821bb91ca4950dc2b817f2)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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1241 val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1242
1243 for(i <- 0 until CommitWidth) {
1244 val idx = deqPtrVec(i).value
1245 wdata(i) := debug_exuData(idx)
1246 wpc(i) := SignExt(commitDebugUop(i).cf.pc, XLEN)
1247 }
1248
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 1232 unchanged lines hidden (view full) ---

1241 val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
1242
1243 for(i <- 0 until CommitWidth) {
1244 val idx = deqPtrVec(i).value
1245 wdata(i) := debug_exuData(idx)
1246 wpc(i) := SignExt(commitDebugUop(i).cf.pc, XLEN)
1247 }
1248
1249 if (env.EnableDifftest) {
1250 for (i <- 0 until CommitWidth) {
1251 val difftest = Module(new DifftestInstrCommit)
1252 // assgin default value
1253 difftest.io := DontCare
1254
1255 difftest.io.clock := clock
1256 difftest.io.coreid := io.hartId
1257 difftest.io.index := i.U
1258
1259 val ptr = deqPtrVec(i).value
1260 val uop = commitDebugUop(i)
1261 val exuOut = debug_exuDebug(ptr)
1262 val exuData = debug_exuData(ptr)
1263 difftest.io.valid := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.isCommit)))
1264 difftest.io.pc := RegNext(RegNext(RegNext(SignExt(uop.cf.pc, XLEN))))
1265 difftest.io.instr := RegNext(RegNext(RegNext(uop.cf.instr)))
1266 difftest.io.robIdx := RegNext(RegNext(RegNext(ZeroExt(ptr, 10))))
1267 difftest.io.lqIdx := RegNext(RegNext(RegNext(ZeroExt(uop.lqIdx.value, 7))))
1268 difftest.io.sqIdx := RegNext(RegNext(RegNext(ZeroExt(uop.sqIdx.value, 7))))
1269 difftest.io.isLoad := RegNext(RegNext(RegNext(io.commits.info(i).commitType === CommitType.LOAD)))
1270 difftest.io.isStore := RegNext(RegNext(RegNext(io.commits.info(i).commitType === CommitType.STORE)))
1271 difftest.io.special := RegNext(RegNext(RegNext(CommitType.isFused(io.commits.info(i).commitType))))
1272 // when committing an eliminated move instruction,
1273 // we must make sure that skip is properly set to false (output from EXU is random value)
1274 difftest.io.skip := RegNext(RegNext(RegNext(Mux(uop.eliminatedMove, false.B, exuOut.isMMIO || exuOut.isPerfCnt))))
1275 difftest.io.isRVC := RegNext(RegNext(RegNext(uop.cf.pd.isRVC)))
1276 difftest.io.rfwen := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.info(i).rfWen && io.commits.info(i).ldest =/= 0.U)))
1277 difftest.io.fpwen := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.info(i).fpWen)))
1278 difftest.io.wpdest := RegNext(RegNext(RegNext(io.commits.info(i).pdest)))
1279 difftest.io.wdest := RegNext(RegNext(RegNext(io.commits.info(i).ldest)))
1280
1281 // // runahead commit hint
1282 // val runahead_commit = Module(new DifftestRunaheadCommitEvent)
1283 // runahead_commit.io.clock := clock
1284 // runahead_commit.io.coreid := io.hartId
1285 // runahead_commit.io.index := i.U
1286 // runahead_commit.io.valid := difftest.io.valid &&
1287 // (commitBranchValid(i) || commitIsStore(i))
1288 // // TODO: is branch or store
1289 // runahead_commit.io.pc := difftest.io.pc
1290 }
1291 }
1292 else if (env.AlwaysBasicDiff) {
1249 if (env.EnableDifftest || env.AlwaysBasicDiff) {
1293 // These are the structures used by difftest only and should be optimized after synthesis.
1294 val dt_eliminatedMove = Mem(RobSize, Bool())
1295 val dt_isRVC = Mem(RobSize, Bool())
1296 val dt_exuDebug = Reg(Vec(RobSize, new DebugBundle))
1297 for (i <- 0 until RenameWidth) {
1298 when (canEnqueue(i)) {
1299 dt_eliminatedMove(allocatePtrVec(i).value) := io.enq.req(i).bits.eliminatedMove
1300 dt_isRVC(allocatePtrVec(i).value) := io.enq.req(i).bits.cf.pd.isRVC
1301 }
1302 }
1303 for (wb <- exuWriteback) {
1304 when (wb.valid) {
1305 val wbIdx = wb.bits.uop.robIdx.value
1306 dt_exuDebug(wbIdx) := wb.bits.debug
1307 }
1308 }
1250 // These are the structures used by difftest only and should be optimized after synthesis.
1251 val dt_eliminatedMove = Mem(RobSize, Bool())
1252 val dt_isRVC = Mem(RobSize, Bool())
1253 val dt_exuDebug = Reg(Vec(RobSize, new DebugBundle))
1254 for (i <- 0 until RenameWidth) {
1255 when (canEnqueue(i)) {
1256 dt_eliminatedMove(allocatePtrVec(i).value) := io.enq.req(i).bits.eliminatedMove
1257 dt_isRVC(allocatePtrVec(i).value) := io.enq.req(i).bits.cf.pd.isRVC
1258 }
1259 }
1260 for (wb <- exuWriteback) {
1261 when (wb.valid) {
1262 val wbIdx = wb.bits.uop.robIdx.value
1263 dt_exuDebug(wbIdx) := wb.bits.debug
1264 }
1265 }
1309 // Always instantiate basic difftest modules.
1310 for (i <- 0 until CommitWidth) {
1311 val commitInfo = io.commits.info(i)
1312 val ptr = deqPtrVec(i).value
1313 val exuOut = dt_exuDebug(ptr)
1314 val eliminatedMove = dt_eliminatedMove(ptr)
1315 val isRVC = dt_isRVC(ptr)
1316
1266 for (i <- 0 until CommitWidth) {
1267 val commitInfo = io.commits.info(i)
1268 val ptr = deqPtrVec(i).value
1269 val exuOut = dt_exuDebug(ptr)
1270 val eliminatedMove = dt_eliminatedMove(ptr)
1271 val isRVC = dt_isRVC(ptr)
1272
1317 val difftest = Module(new DifftestBasicInstrCommit)
1318 difftest.io.clock := clock
1319 difftest.io.coreid := io.hartId
1320 difftest.io.index := i.U
1321 difftest.io.valid := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.isCommit)))
1322 difftest.io.special := RegNext(RegNext(RegNext(CommitType.isFused(commitInfo.commitType))))
1323 difftest.io.skip := RegNext(RegNext(RegNext(Mux(eliminatedMove, false.B, exuOut.isMMIO || exuOut.isPerfCnt))))
1324 difftest.io.isRVC := RegNext(RegNext(RegNext(isRVC)))
1325 difftest.io.rfwen := RegNext(RegNext(RegNext(io.commits.commitValid(i) && commitInfo.rfWen && commitInfo.ldest =/= 0.U)))
1326 difftest.io.fpwen := RegNext(RegNext(RegNext(io.commits.commitValid(i) && commitInfo.fpWen)))
1327 difftest.io.wpdest := RegNext(RegNext(RegNext(commitInfo.pdest)))
1328 difftest.io.wdest := RegNext(RegNext(RegNext(commitInfo.ldest)))
1273 val difftest = DifftestModule(new DiffInstrCommit(NRPhyRegs), delay = 3, dontCare = true)
1274 difftest.clock := clock
1275 difftest.coreid := io.hartId
1276 difftest.index := i.U
1277 difftest.valid := io.commits.commitValid(i) && io.commits.isCommit
1278 difftest.skip := Mux(eliminatedMove, false.B, exuOut.isMMIO || exuOut.isPerfCnt)
1279 difftest.isRVC := isRVC
1280 difftest.rfwen := io.commits.commitValid(i) && commitInfo.rfWen && commitInfo.ldest =/= 0.U
1281 difftest.fpwen := io.commits.commitValid(i) && commitInfo.fpWen
1282 difftest.wpdest := commitInfo.pdest
1283 difftest.wdest := commitInfo.ldest
1284 difftest.nFused := Mux(CommitType.isFused(commitInfo.commitType), 1.U, 0.U)
1285
1286 if (env.EnableDifftest) {
1287 val uop = commitDebugUop(i)
1288 difftest.pc := SignExt(uop.cf.pc, XLEN)
1289 difftest.instr := uop.cf.instr
1290 difftest.robIdx := ZeroExt(ptr, 10)
1291 difftest.lqIdx := ZeroExt(uop.lqIdx.value, 7)
1292 difftest.sqIdx := ZeroExt(uop.sqIdx.value, 7)
1293 difftest.isLoad := io.commits.info(i).commitType === CommitType.LOAD
1294 difftest.isStore := io.commits.info(i).commitType === CommitType.STORE
1295 }
1329 }
1330 }
1331
1332 if (env.EnableDifftest) {
1333 for (i <- 0 until CommitWidth) {
1296 }
1297 }
1298
1299 if (env.EnableDifftest) {
1300 for (i <- 0 until CommitWidth) {
1334 val difftest = Module(new DifftestLoadEvent)
1335 difftest.io.clock := clock
1336 difftest.io.coreid := io.hartId
1337 difftest.io.index := i.U
1301 val difftest = DifftestModule(new DiffLoadEvent, delay = 3)
1302 difftest.clock := clock
1303 difftest.coreid := io.hartId
1304 difftest.index := i.U
1338
1339 val ptr = deqPtrVec(i).value
1340 val uop = commitDebugUop(i)
1341 val exuOut = debug_exuDebug(ptr)
1305
1306 val ptr = deqPtrVec(i).value
1307 val uop = commitDebugUop(i)
1308 val exuOut = debug_exuDebug(ptr)
1342 difftest.io.valid := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.isCommit)))
1343 difftest.io.paddr := RegNext(RegNext(RegNext(exuOut.paddr)))
1344 difftest.io.opType := RegNext(RegNext(RegNext(uop.ctrl.fuOpType)))
1345 difftest.io.fuType := RegNext(RegNext(RegNext(uop.ctrl.fuType)))
1309 difftest.valid := io.commits.commitValid(i) && io.commits.isCommit
1310 difftest.paddr := exuOut.paddr
1311 difftest.opType := uop.ctrl.fuOpType
1312 difftest.fuType := uop.ctrl.fuType
1346 }
1347 }
1348
1313 }
1314 }
1315
1349 // Always instantiate basic difftest modules.
1350 if (env.EnableDifftest) {
1316 if (env.EnableDifftest || env.AlwaysBasicDiff) {
1351 val dt_isXSTrap = Mem(RobSize, Bool())
1352 for (i <- 0 until RenameWidth) {
1353 when (canEnqueue(i)) {
1354 dt_isXSTrap(allocatePtrVec(i).value) := io.enq.req(i).bits.ctrl.isXSTrap
1355 }
1356 }
1317 val dt_isXSTrap = Mem(RobSize, Bool())
1318 for (i <- 0 until RenameWidth) {
1319 when (canEnqueue(i)) {
1320 dt_isXSTrap(allocatePtrVec(i).value) := io.enq.req(i).bits.ctrl.isXSTrap
1321 }
1322 }
1357 val trapVec = io.commits.commitValid.zip(deqPtrVec).map{ case (v, d) => io.commits.isCommit && v && dt_isXSTrap(d.value) }
1358 val hitTrap = trapVec.reduce(_||_)
1359 val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
1360 val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1)), XLEN)
1361 val difftest = Module(new DifftestTrapEvent)
1362 difftest.io.clock := clock
1363 difftest.io.coreid := io.hartId
1364 difftest.io.valid := hitTrap
1365 difftest.io.code := trapCode
1366 difftest.io.pc := trapPC
1367 difftest.io.cycleCnt := timer
1368 difftest.io.instrCnt := instrCnt
1369 difftest.io.hasWFI := hasWFI
1370 }
1371 else if (env.AlwaysBasicDiff) {
1372 val dt_isXSTrap = Mem(RobSize, Bool())
1373 for (i <- 0 until RenameWidth) {
1374 when (canEnqueue(i)) {
1375 dt_isXSTrap(allocatePtrVec(i).value) := io.enq.req(i).bits.ctrl.isXSTrap
1376 }
1323 val trapVec = io.commits.commitValid.zip(deqPtrVec).map{ case (v, d) =>
1324 io.commits.isCommit && v && dt_isXSTrap(d.value)
1377 }
1325 }
1378 val trapVec = io.commits.commitValid.zip(deqPtrVec).map{ case (v, d) => io.commits.isCommit && v && dt_isXSTrap(d.value) }
1379 val hitTrap = trapVec.reduce(_||_)
1326 val hitTrap = trapVec.reduce(_||_)
1380 val difftest = Module(new DifftestBasicTrapEvent)
1381 difftest.io.clock := clock
1382 difftest.io.coreid := io.hartId
1383 difftest.io.valid := hitTrap
1384 difftest.io.cycleCnt := timer
1385 difftest.io.instrCnt := instrCnt
1327 val difftest = DifftestModule(new DiffTrapEvent, dontCare = true)
1328 difftest.clock := clock
1329 difftest.coreid := io.hartId
1330 difftest.hasTrap := hitTrap
1331 difftest.cycleCnt := timer
1332 difftest.instrCnt := instrCnt
1333 difftest.hasWFI := hasWFI
1334
1335 if (env.EnableDifftest) {
1336 val trapCode = PriorityMux(wdata.zip(trapVec).map(x => x._2 -> x._1))
1337 val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1)), XLEN)
1338 difftest.code := trapCode
1339 difftest.pc := trapPC
1340 }
1386 }
1387
1388 val validEntriesBanks = (0 until (RobSize + 31) / 32).map(i => RegNext(PopCount(valid.drop(i * 32).take(32))))
1389 val validEntries = RegNext(VecInit(validEntriesBanks).reduceTree(_ +& _))
1390 val commitMoveVec = VecInit(io.commits.commitValid.zip(commitIsMove).map{ case (v, m) => v && m })
1391 val commitLoadVec = VecInit(commitLoadValid)
1392 val commitBranchVec = VecInit(commitBranchValid)
1393 val commitLoadWaitVec = VecInit(commitLoadValid.zip(commitLoadWaitBit).map{ case (v, w) => v && w })

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1342
1343 val validEntriesBanks = (0 until (RobSize + 31) / 32).map(i => RegNext(PopCount(valid.drop(i * 32).take(32))))
1344 val validEntries = RegNext(VecInit(validEntriesBanks).reduceTree(_ +& _))
1345 val commitMoveVec = VecInit(io.commits.commitValid.zip(commitIsMove).map{ case (v, m) => v && m })
1346 val commitLoadVec = VecInit(commitLoadValid)
1347 val commitBranchVec = VecInit(commitBranchValid)
1348 val commitLoadWaitVec = VecInit(commitLoadValid.zip(commitLoadWaitBit).map{ case (v, w) => v && w })

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