CSR.scala (c61abc0c251b288ded38101b3c7ca47a9357e2ef) CSR.scala (7d45a146d3c44839ba821bb91ca4950dc2b817f2)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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23import freechips.rocketchip.util._
24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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23import freechips.rocketchip.util._
24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
31import xiangshan.backend.Bundles.ExceptionInfo
32
33// Trigger Tdata1 bundles
34trait HasTriggerConst {
35 def I_Trigger = 0.U
36 def S_Trigger = 1.U
37 def L_Trigger = 2.U
38 def GenESL(triggerType: UInt) = Cat((triggerType === I_Trigger), (triggerType === S_Trigger), (triggerType === L_Trigger))
39}

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62
63class FpuCsrIO extends Bundle {
64 val fflags = Output(Valid(UInt(5.W)))
65 val isIllegal = Output(Bool())
66 val dirty_fs = Output(Bool())
67 val frm = Input(UInt(3.W))
68}
69
31
32// Trigger Tdata1 bundles
33trait HasTriggerConst {
34 def I_Trigger = 0.U
35 def S_Trigger = 1.U
36 def L_Trigger = 2.U
37 def GenESL(triggerType: UInt) = Cat((triggerType === I_Trigger), (triggerType === S_Trigger), (triggerType === L_Trigger))
38}

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61
62class FpuCsrIO extends Bundle {
63 val fflags = Output(Valid(UInt(5.W)))
64 val isIllegal = Output(Bool())
65 val dirty_fs = Output(Bool())
66 val frm = Input(UInt(3.W))
67}
68
70class VpuCsrIO(implicit p: Parameters) extends XSBundle {
71 val vstart = Input(UInt(XLEN.W))
72 val vxsat = Input(UInt(1.W))
73 val vxrm = Input(UInt(2.W))
74 val vcsr = Input(UInt(XLEN.W))
75 val vl = Input(UInt(XLEN.W))
76 val vtype = Input(UInt(XLEN.W))
77 val vlenb = Input(UInt(XLEN.W))
78
79 val vill = Input(UInt(1.W))
80 val vma = Input(UInt(1.W))
81 val vta = Input(UInt(1.W))
82 val vsew = Input(UInt(3.W))
83 val vlmul = Input(UInt(3.W))
84
69
85 val set_vstart = Output(Valid(UInt(XLEN.W)))
86 val set_vl = Output(Valid(UInt(XLEN.W)))
87 val set_vtype = Output(Valid(UInt(XLEN.W)))
88 val set_vxsat = Output(Valid(UInt(1.W)))
89
90 val dirty_vs = Output(Bool())
91}
92
93
94class PerfCounterIO(implicit p: Parameters) extends XSBundle {
95 val perfEventsFrontend = Vec(numCSRPCntFrontend, new PerfEvent)
96 val perfEventsCtrl = Vec(numCSRPCntCtrl, new PerfEvent)
97 val perfEventsLsu = Vec(numCSRPCntLsu, new PerfEvent)
98 val perfEventsHc = Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)
99 val retiredInstr = UInt(3.W)
100 val frontendInfo = new Bundle {
101 val ibufFull = Bool()

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128
129class CSRFileIO(implicit p: Parameters) extends XSBundle {
130 val hartId = Input(UInt(8.W))
131 // output (for func === CSROpType.jmp)
132 val perf = Input(new PerfCounterIO)
133 val isPerfCnt = Output(Bool())
134 // to FPU
135 val fpu = Flipped(new FpuCsrIO)
70class PerfCounterIO(implicit p: Parameters) extends XSBundle {
71 val perfEventsFrontend = Vec(numCSRPCntFrontend, new PerfEvent)
72 val perfEventsCtrl = Vec(numCSRPCntCtrl, new PerfEvent)
73 val perfEventsLsu = Vec(numCSRPCntLsu, new PerfEvent)
74 val perfEventsHc = Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)
75 val retiredInstr = UInt(3.W)
76 val frontendInfo = new Bundle {
77 val ibufFull = Bool()

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104
105class CSRFileIO(implicit p: Parameters) extends XSBundle {
106 val hartId = Input(UInt(8.W))
107 // output (for func === CSROpType.jmp)
108 val perf = Input(new PerfCounterIO)
109 val isPerfCnt = Output(Bool())
110 // to FPU
111 val fpu = Flipped(new FpuCsrIO)
136 // to VPU
137 val vpu = Flipped(new VpuCsrIO)
138 // from rob
139 val exception = Flipped(ValidIO(new ExceptionInfo))
140 // to ROB
141 val isXRet = Output(Bool())
142 val trapTarget = Output(UInt(VAddrBits.W))
143 val interrupt = Output(Bool())
144 val wfi_event = Output(Bool())
145 // from LSQ

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154 // to Fence to disable sfence
155 val disableSfence = Output(Bool())
156 // Custom microarchiture ctrl signal
157 val customCtrl = Output(new CustomCSRCtrlIO)
158 // distributed csr write
159 val distributedUpdate = Vec(2, Flipped(new DistributedCSRUpdateReq))
160}
161
112 // from rob
113 val exception = Flipped(ValidIO(new ExceptionInfo))
114 // to ROB
115 val isXRet = Output(Bool())
116 val trapTarget = Output(UInt(VAddrBits.W))
117 val interrupt = Output(Bool())
118 val wfi_event = Output(Bool())
119 // from LSQ

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128 // to Fence to disable sfence
129 val disableSfence = Output(Bool())
130 // Custom microarchiture ctrl signal
131 val customCtrl = Output(new CustomCSRCtrlIO)
132 // distributed csr write
133 val distributedUpdate = Vec(2, Flipped(new DistributedCSRUpdateReq))
134}
135
162class VtypeStruct(implicit p: Parameters) extends XSBundle {
163 val vill = UInt(1.W)
164 val reserved = UInt((XLEN - 9).W)
165 val vma = UInt(1.W)
166 val vta = UInt(1.W)
167 val vsew = UInt(3.W)
168 val vlmul = UInt(3.W)
169}
170
171class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
172 with HasCSRConst
173 with PMPMethod
174 with PMAMethod
175 with HasTriggerConst
176 with HasXSParameter
136class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMPMethod with PMAMethod with HasTriggerConst
177{
137{
178 val csrio = io.csrio.get
138 val csrio = IO(new CSRFileIO)
179
139
140 val cfIn = io.in.bits.uop.cf
141 val cfOut = Wire(new CtrlFlow)
142 cfOut := cfIn
180 val flushPipe = Wire(Bool())
181
182 val (valid, src1, src2, func) = (
183 io.in.valid,
143 val flushPipe = Wire(Bool())
144
145 val (valid, src1, src2, func) = (
146 io.in.valid,
184 io.in.bits.data.src(0),
185 io.in.bits.data.imm,
186 io.in.bits.ctrl.fuOpType
147 io.in.bits.src(0),
148 io.in.bits.uop.ctrl.imm,
149 io.in.bits.uop.ctrl.fuOpType
187 )
188
189 // CSR define
190
191 class Priv extends Bundle {
192 val m = Output(Bool())
193 val h = Output(Bool())
194 val s = Output(Bool())
195 val u = Output(Bool())
196 }
197
150 )
151
152 // CSR define
153
154 class Priv extends Bundle {
155 val m = Output(Bool())
156 val h = Output(Bool())
157 val s = Output(Bool())
158 val u = Output(Bool())
159 }
160
161 val csrNotImplemented = RegInit(UInt(XLEN.W), 0.U)
162
198 class DcsrStruct extends Bundle {
199 val xdebugver = Output(UInt(2.W))
200 val zero4 = Output(UInt(2.W))
201 val zero3 = Output(UInt(12.W))
202 val ebreakm = Output(Bool())
203 val ebreakh = Output(Bool())
204 val ebreaks = Output(Bool())
205 val ebreaku = Output(Bool())

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228 val tw = Output(UInt(1.W))
229 val tvm = Output(UInt(1.W))
230 val mxr = Output(UInt(1.W))
231 val sum = Output(UInt(1.W))
232 val mprv = Output(UInt(1.W))
233 val xs = Output(UInt(2.W))
234 val fs = Output(UInt(2.W))
235 val mpp = Output(UInt(2.W))
163 class DcsrStruct extends Bundle {
164 val xdebugver = Output(UInt(2.W))
165 val zero4 = Output(UInt(2.W))
166 val zero3 = Output(UInt(12.W))
167 val ebreakm = Output(Bool())
168 val ebreakh = Output(Bool())
169 val ebreaks = Output(Bool())
170 val ebreaku = Output(Bool())

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193 val tw = Output(UInt(1.W))
194 val tvm = Output(UInt(1.W))
195 val mxr = Output(UInt(1.W))
196 val sum = Output(UInt(1.W))
197 val mprv = Output(UInt(1.W))
198 val xs = Output(UInt(2.W))
199 val fs = Output(UInt(2.W))
200 val mpp = Output(UInt(2.W))
236 val vs = Output(UInt(2.W))
201 val hpp = Output(UInt(2.W))
237 val spp = Output(UInt(1.W))
238 val pie = new Priv
239 val ie = new Priv
240 assert(this.getWidth == XLEN)
241
242 def ube = pie.h // a little ugly
243 def ube_(r: UInt): Unit = {
244 pie.h := r(0)

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397 val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
398
399 def getMisaMxl(mxl: BigInt): BigInt = mxl << (XLEN - 2)
400 def getMisaExt(ext: Char): Long = 1 << (ext.toInt - 'a'.toInt)
401 var extList = List('a', 's', 'i', 'u')
402 if (HasMExtension) { extList = extList :+ 'm' }
403 if (HasCExtension) { extList = extList :+ 'c' }
404 if (HasFPU) { extList = extList ++ List('f', 'd') }
202 val spp = Output(UInt(1.W))
203 val pie = new Priv
204 val ie = new Priv
205 assert(this.getWidth == XLEN)
206
207 def ube = pie.h // a little ugly
208 def ube_(r: UInt): Unit = {
209 pie.h := r(0)

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362 val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
363
364 def getMisaMxl(mxl: BigInt): BigInt = mxl << (XLEN - 2)
365 def getMisaExt(ext: Char): Long = 1 << (ext.toInt - 'a'.toInt)
366 var extList = List('a', 's', 'i', 'u')
367 if (HasMExtension) { extList = extList :+ 'm' }
368 if (HasCExtension) { extList = extList :+ 'c' }
369 if (HasFPU) { extList = extList ++ List('f', 'd') }
405 if (HasVPU) { extList = extList :+ 'v' }
406 val misaInitVal = getMisaMxl(2) | extList.foldLeft(0L)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
407 val misa = RegInit(UInt(XLEN.W), misaInitVal.U)
370 val misaInitVal = getMisaMxl(2) | extList.foldLeft(0L)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
371 val misa = RegInit(UInt(XLEN.W), misaInitVal.U)
408 println(s"[CSR] supported isa ext: $extList")
409
410 // MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
411 // (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
412
413 val mvendorid = RegInit(UInt(XLEN.W), 0.U) // this is a non-commercial implementation
414 val marchid = RegInit(UInt(XLEN.W), 25.U) // architecture id for XiangShan is 25; see https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
415 val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation
416 val mhartid = Reg(UInt(XLEN.W)) // the hardware thread running the code

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430 // | tw |
431 // | tvm |
432 // | mxr |
433 // | sum |
434 // | mprv |
435 // | xs | 00 |
436 // | fs | 01 |
437 // | mpp | 00 |
372
373 // MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
374 // (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
375
376 val mvendorid = RegInit(UInt(XLEN.W), 0.U) // this is a non-commercial implementation
377 val marchid = RegInit(UInt(XLEN.W), 25.U) // architecture id for XiangShan is 25; see https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
378 val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation
379 val mhartid = Reg(UInt(XLEN.W)) // the hardware thread running the code

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393 // | tw |
394 // | tvm |
395 // | mxr |
396 // | sum |
397 // | mprv |
398 // | xs | 00 |
399 // | fs | 01 |
400 // | mpp | 00 |
438 // | vs | 00 |
401 // | hpp | 00 |
439 // | spp | 0 |
440 // | pie | 0000 | pie.h is used as UBE
441 // | ie | 0000 | uie hardlinked to 0, as N ext is not implemented
442
443 val mstatusStruct = mstatus.asTypeOf(new MstatusStruct)
444 def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
445 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
446 val mstatusNew = Cat(mstatusOld.xs === "b11".U || mstatusOld.fs === "b11".U, mstatus(XLEN-2, 0))

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582 // Bit 6 : Enable cache error after reset (CE).
583 // Bit 7 : Enable uncache write outstanding (O).
584 // Others : Reserved.
585
586 val smblockctl_init_val =
587 (0xf & StoreBufferThreshold) |
588 (EnableLdVioCheckAfterReset.toInt << 4) |
589 (EnableSoftPrefetchAfterReset.toInt << 5) |
402 // | spp | 0 |
403 // | pie | 0000 | pie.h is used as UBE
404 // | ie | 0000 | uie hardlinked to 0, as N ext is not implemented
405
406 val mstatusStruct = mstatus.asTypeOf(new MstatusStruct)
407 def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
408 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
409 val mstatusNew = Cat(mstatusOld.xs === "b11".U || mstatusOld.fs === "b11".U, mstatus(XLEN-2, 0))

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545 // Bit 6 : Enable cache error after reset (CE).
546 // Bit 7 : Enable uncache write outstanding (O).
547 // Others : Reserved.
548
549 val smblockctl_init_val =
550 (0xf & StoreBufferThreshold) |
551 (EnableLdVioCheckAfterReset.toInt << 4) |
552 (EnableSoftPrefetchAfterReset.toInt << 5) |
590 (EnableCacheErrorAfterReset.toInt << 6) |
553 (EnableCacheErrorAfterReset.toInt << 6)
591 (EnableUncacheWriteOutstanding.toInt << 7)
592 val smblockctl = RegInit(UInt(XLEN.W), smblockctl_init_val.U)
593 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
594 // bits 4: enable load load violation check
595 csrio.customCtrl.ldld_vio_check_enable := smblockctl(4)
596 csrio.customCtrl.soft_prefetch_enable := smblockctl(5)
597 csrio.customCtrl.cache_error_enable := smblockctl(6)
598 csrio.customCtrl.uncache_write_outstanding_enable := smblockctl(7)

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656 }
657
658 val fcsrMapping = Map(
659 MaskedRegMap(Fflags, fcsr, wfn = fflags_wfn(update = false), rfn = fflags_rfn),
660 MaskedRegMap(Frm, fcsr, wfn = frm_wfn, rfn = frm_rfn),
661 MaskedRegMap(Fcsr, fcsr, wfn = fcsr_wfn)
662 )
663
554 (EnableUncacheWriteOutstanding.toInt << 7)
555 val smblockctl = RegInit(UInt(XLEN.W), smblockctl_init_val.U)
556 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
557 // bits 4: enable load load violation check
558 csrio.customCtrl.ldld_vio_check_enable := smblockctl(4)
559 csrio.customCtrl.soft_prefetch_enable := smblockctl(5)
560 csrio.customCtrl.cache_error_enable := smblockctl(6)
561 csrio.customCtrl.uncache_write_outstanding_enable := smblockctl(7)

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619 }
620
621 val fcsrMapping = Map(
622 MaskedRegMap(Fflags, fcsr, wfn = fflags_wfn(update = false), rfn = fflags_rfn),
623 MaskedRegMap(Frm, fcsr, wfn = frm_wfn, rfn = frm_rfn),
624 MaskedRegMap(Fcsr, fcsr, wfn = fcsr_wfn)
625 )
626
664 // Vector extension CSRs
665 val vstart = Reg(UInt(XLEN.W))
666 val vcsr = RegInit(0.U(XLEN.W))
667 val vl = Reg(UInt(XLEN.W))
668 val vtype = Reg(UInt(XLEN.W))
669 val vlenb = RegInit(0.U(XLEN.W))
670
671 // set mstatus->sd and mstatus->vs when true
672 val csrw_dirty_vs_state = WireInit(false.B)
673
674 // vcsr is mapped to vxrm and vxsat
675 class VcsrStruct extends Bundle {
676 val reserved = UInt((XLEN-3).W)
677 val vxrm = UInt(2.W)
678 val vxsat = UInt(1.W)
679 assert(this.getWidth == XLEN)
680 }
681
682 def vxrm_wfn(wdata: UInt): UInt = {
683 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
684 csrw_dirty_vs_state := true.B
685 vcsrOld.vxrm := wdata(1,0)
686 vcsrOld.asUInt
687 }
688 def vxrm_rfn(rdata: UInt): UInt = rdata(2,1)
689
690 def vxsat_wfn(update: Boolean)(wdata: UInt): UInt = {
691 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
692 val vcsrNew = WireInit(vcsrOld)
693 csrw_dirty_vs_state := true.B
694 if (update) {
695 vcsrNew.vxsat := wdata(0) | vcsrOld.vxsat
696 } else {
697 vcsrNew.vxsat := wdata(0)
698 }
699 vcsrNew.asUInt
700 }
701 def vxsat_rfn(rdata: UInt): UInt = rdata(0)
702
703 def vcsr_wfn(wdata: UInt): UInt = {
704 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
705 csrw_dirty_vs_state := true.B
706 vcsrOld.vxrm := wdata.asTypeOf(vcsrOld).vxrm
707 vcsrOld.vxsat := wdata.asTypeOf(vcsrOld).vxsat
708 vcsrOld.asUInt
709 }
710
711 val vcsrMapping = Map(
712 MaskedRegMap(Vstart, vstart),
713 MaskedRegMap(Vxrm, vcsr, wfn = vxrm_wfn, rfn = vxrm_rfn),
714 MaskedRegMap(Vxsat, vcsr, wfn = vxsat_wfn(false), rfn = vxsat_rfn),
715 MaskedRegMap(Vcsr, vcsr, wfn = vcsr_wfn),
716 MaskedRegMap(Vl, vl),
717 MaskedRegMap(Vtype, vtype),
718 MaskedRegMap(Vlenb, vlenb),
719 )
720
721 // Hart Priviledge Mode
722 val priviledgeMode = RegInit(UInt(2.W), ModeM)
723
724 //val perfEventscounten = List.fill(nrPerfCnts)(RegInit(false(Bool())))
725 // Perf Counter
726 val nrPerfCnts = 29 // 3...31
727 val priviledgeModeOH = UIntToOH(priviledgeMode)
728 val perfEventscounten = RegInit(0.U.asTypeOf(Vec(nrPerfCnts, Bool())))

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867 )
868 }}
869
870 val mapping = basicPrivMapping ++
871 perfCntMapping ++
872 pmpMapping ++
873 pmaMapping ++
874 (if (HasFPU) fcsrMapping else Nil) ++
627 // Hart Priviledge Mode
628 val priviledgeMode = RegInit(UInt(2.W), ModeM)
629
630 //val perfEventscounten = List.fill(nrPerfCnts)(RegInit(false(Bool())))
631 // Perf Counter
632 val nrPerfCnts = 29 // 3...31
633 val priviledgeModeOH = UIntToOH(priviledgeMode)
634 val perfEventscounten = RegInit(0.U.asTypeOf(Vec(nrPerfCnts, Bool())))

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773 )
774 }}
775
776 val mapping = basicPrivMapping ++
777 perfCntMapping ++
778 pmpMapping ++
779 pmaMapping ++
780 (if (HasFPU) fcsrMapping else Nil) ++
875 (if (HasVPU) vcsrMapping else Nil) ++
876 (if (HasCustomCSRCacheOp) cacheopMapping else Nil)
877
878 val addr = src2(11, 0)
879 val csri = ZeroExt(src2(16, 12), XLEN)
880 val rdata = Wire(UInt(XLEN.W))
881 val wdata = LookupTree(func, List(
882 CSROpType.wrt -> src1,
883 CSROpType.set -> (rdata | src1),

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904 val wen = valid && CSROpType.needAccess(func) && (addr=/=Satp.U || satpLegalMode)
905 val dcsrPermitted = dcsrPermissionCheck(addr, false.B, debugMode)
906 val triggerPermitted = triggerPermissionCheck(addr, true.B, debugMode) // todo dmode
907 val modePermitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode) && dcsrPermitted && triggerPermitted
908 val perfcntPermitted = perfcntPermissionCheck(addr, priviledgeMode, mcounteren, scounteren)
909 val permitted = Mux(addrInPerfCnt, perfcntPermitted, modePermitted) && accessPermitted
910
911 MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
781 (if (HasCustomCSRCacheOp) cacheopMapping else Nil)
782
783 val addr = src2(11, 0)
784 val csri = ZeroExt(src2(16, 12), XLEN)
785 val rdata = Wire(UInt(XLEN.W))
786 val wdata = LookupTree(func, List(
787 CSROpType.wrt -> src1,
788 CSROpType.set -> (rdata | src1),

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809 val wen = valid && CSROpType.needAccess(func) && (addr=/=Satp.U || satpLegalMode)
810 val dcsrPermitted = dcsrPermissionCheck(addr, false.B, debugMode)
811 val triggerPermitted = triggerPermissionCheck(addr, true.B, debugMode) // todo dmode
812 val modePermitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode) && dcsrPermitted && triggerPermitted
813 val perfcntPermitted = perfcntPermissionCheck(addr, priviledgeMode, mcounteren, scounteren)
814 val permitted = Mux(addrInPerfCnt, perfcntPermitted, modePermitted) && accessPermitted
815
816 MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
912 io.out.bits.res.data := rdata
913 io.out.bits.ctrl.flushPipe.get := flushPipe
914 connectNonPipedCtrlSingal
817 io.out.bits.data := rdata
818 io.out.bits.uop := io.in.bits.uop
819 io.out.bits.uop.cf := cfOut
820 io.out.bits.uop.ctrl.flushPipe := flushPipe
915
916 // send distribute csr a w signal
917 csrio.customCtrl.distribute_csr.w.valid := wen && permitted
918 csrio.customCtrl.distribute_csr.w.bits.data := wdata
919 csrio.customCtrl.distribute_csr.w.bits.addr := addr
920
921 // Fix Mip/Sip write
922 val fixMapping = Map(

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932 CSROpType.seti -> (rdataFix | csri),
933 CSROpType.clri -> (rdataFix & (~csri).asUInt)
934 ))
935 MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
936
937 when (RegNext(csrio.fpu.fflags.valid)) {
938 fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
939 }
821
822 // send distribute csr a w signal
823 csrio.customCtrl.distribute_csr.w.valid := wen && permitted
824 csrio.customCtrl.distribute_csr.w.bits.data := wdata
825 csrio.customCtrl.distribute_csr.w.bits.addr := addr
826
827 // Fix Mip/Sip write
828 val fixMapping = Map(

--- 9 unchanged lines hidden (view full) ---

838 CSROpType.seti -> (rdataFix | csri),
839 CSROpType.clri -> (rdataFix & (~csri).asUInt)
840 ))
841 MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
842
843 when (RegNext(csrio.fpu.fflags.valid)) {
844 fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
845 }
940 when(RegNext(csrio.vpu.set_vxsat.valid)) {
941 vcsr := vxsat_wfn(update = true)(RegNext(csrio.vpu.set_vxsat.bits))
942 }
943 // set fs and sd in mstatus
944 when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
945 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
946 mstatusNew.fs := "b11".U
947 mstatusNew.sd := true.B
948 mstatus := mstatusNew.asUInt
949 }
950 csrio.fpu.frm := fcsr.asTypeOf(new FcsrStruct).frm
951
846 // set fs and sd in mstatus
847 when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
848 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
849 mstatusNew.fs := "b11".U
850 mstatusNew.sd := true.B
851 mstatus := mstatusNew.asUInt
852 }
853 csrio.fpu.frm := fcsr.asTypeOf(new FcsrStruct).frm
854
952 when (RegNext(csrio.vpu.set_vstart.valid)) {
953 vstart := RegNext(csrio.vpu.set_vstart.bits)
954 }
955 when (RegNext(csrio.vpu.set_vtype.valid)) {
956 vtype := RegNext(csrio.vpu.set_vtype.bits)
957 }
958 when (RegNext(csrio.vpu.set_vl.valid)) {
959 vl := RegNext(csrio.vpu.set_vl.bits)
960 }
961 // set vs and sd in mstatus
962 // when (csrw_dirty_vs_state || RegNext(csrio.vpu.dirty_vs)) {
963 // val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
964 // mstatusNew.vs := "b11".U
965 // mstatusNew.sd := true.B
966 // mstatus := mstatusNew.asUInt
967 // }
968
969 csrio.vpu.vstart := vstart
970 csrio.vpu.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
971 csrio.vpu.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
972 csrio.vpu.vcsr := vcsr
973 csrio.vpu.vtype := vtype
974 csrio.vpu.vl := vl
975 csrio.vpu.vlenb := vlenb
976 csrio.vpu.vill := vtype.asTypeOf(new VtypeStruct).vill
977 csrio.vpu.vma := vtype.asTypeOf(new VtypeStruct).vma
978 csrio.vpu.vta := vtype.asTypeOf(new VtypeStruct).vta
979 csrio.vpu.vsew := vtype.asTypeOf(new VtypeStruct).vsew
980 csrio.vpu.vlmul := vtype.asTypeOf(new VtypeStruct).vlmul
981
982 // Trigger Ctrl
983 csrio.customCtrl.trigger_enable := tdata1Phy.map{t =>
984 def tdata1 = t.asTypeOf(new TdataBundle)
985 tdata1.m && priviledgeMode === ModeM ||
986 tdata1.s && priviledgeMode === ModeS || tdata1.u && priviledgeMode === ModeU
987 }
988 csrio.customCtrl.frontend_trigger.t.valid := RegNext(wen && (addr === Tdata1.U || addr === Tdata2.U) && TypeLookup(tselectPhy) === I_Trigger)

--- 5 unchanged lines hidden (view full) ---

994 val isEbreak = addr === privEbreak && func === CSROpType.jmp
995 val isEcall = addr === privEcall && func === CSROpType.jmp
996 val isMret = addr === privMret && func === CSROpType.jmp
997 val isSret = addr === privSret && func === CSROpType.jmp
998 val isUret = addr === privUret && func === CSROpType.jmp
999 val isDret = addr === privDret && func === CSROpType.jmp
1000 val isWFI = func === CSROpType.wfi
1001
855
856 // Trigger Ctrl
857 csrio.customCtrl.trigger_enable := tdata1Phy.map{t =>
858 def tdata1 = t.asTypeOf(new TdataBundle)
859 tdata1.m && priviledgeMode === ModeM ||
860 tdata1.s && priviledgeMode === ModeS || tdata1.u && priviledgeMode === ModeU
861 }
862 csrio.customCtrl.frontend_trigger.t.valid := RegNext(wen && (addr === Tdata1.U || addr === Tdata2.U) && TypeLookup(tselectPhy) === I_Trigger)

--- 5 unchanged lines hidden (view full) ---

868 val isEbreak = addr === privEbreak && func === CSROpType.jmp
869 val isEcall = addr === privEcall && func === CSROpType.jmp
870 val isMret = addr === privMret && func === CSROpType.jmp
871 val isSret = addr === privSret && func === CSROpType.jmp
872 val isUret = addr === privUret && func === CSROpType.jmp
873 val isDret = addr === privDret && func === CSROpType.jmp
874 val isWFI = func === CSROpType.wfi
875
1002 XSDebug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", io.in.bits.data.pc.get, addr, rdata, wdata, func)
1003 XSDebug(wen, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.in.bits.data.pc.get, mstatus, mideleg , medeleg, priviledgeMode)
876 XSDebug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", cfIn.pc, addr, rdata, wdata, func)
877 XSDebug(wen, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
1004
1005 // Illegal priviledged operation list
1006 val illegalMret = valid && isMret && priviledgeMode < ModeM
1007 val illegalSret = valid && isSret && priviledgeMode < ModeS
1008 val illegalSModeSret = valid && isSret && priviledgeMode === ModeS && mstatusStruct.tsr.asBool
1009 // When TW=1, then if WFI is executed in any less-privileged mode,
1010 // and it does not complete within an implementation-specific, bounded time limit,
1011 // the WFI instruction causes an illegal instruction exception.

--- 72 unchanged lines hidden (view full) ---

1084 retTarget := uepc(VAddrBits-1, 0)
1085 }
1086
1087 io.in.ready := true.B
1088 io.out.valid := valid
1089
1090 val ebreakCauseException = (priviledgeMode === ModeM && dcsrData.ebreakm) || (priviledgeMode === ModeS && dcsrData.ebreaks) || (priviledgeMode === ModeU && dcsrData.ebreaku)
1091
878
879 // Illegal priviledged operation list
880 val illegalMret = valid && isMret && priviledgeMode < ModeM
881 val illegalSret = valid && isSret && priviledgeMode < ModeS
882 val illegalSModeSret = valid && isSret && priviledgeMode === ModeS && mstatusStruct.tsr.asBool
883 // When TW=1, then if WFI is executed in any less-privileged mode,
884 // and it does not complete within an implementation-specific, bounded time limit,
885 // the WFI instruction causes an illegal instruction exception.

--- 72 unchanged lines hidden (view full) ---

958 retTarget := uepc(VAddrBits-1, 0)
959 }
960
961 io.in.ready := true.B
962 io.out.valid := valid
963
964 val ebreakCauseException = (priviledgeMode === ModeM && dcsrData.ebreakm) || (priviledgeMode === ModeS && dcsrData.ebreaks) || (priviledgeMode === ModeU && dcsrData.ebreaku)
965
1092 val csrExceptionVec = WireInit(0.U.asTypeOf(ExceptionVec()))
966 val csrExceptionVec = WireInit(cfIn.exceptionVec)
1093 csrExceptionVec(breakPoint) := io.in.valid && isEbreak && (ebreakCauseException || debugMode)
1094 csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
1095 csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
1096 csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
1097 // Trigger an illegal instr exception when:
1098 // * unimplemented csr is being read/written
1099 // * csr access is illegal
1100 csrExceptionVec(illegalInstr) := isIllegalAddr || isIllegalAccess || isIllegalPrivOp
967 csrExceptionVec(breakPoint) := io.in.valid && isEbreak && (ebreakCauseException || debugMode)
968 csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
969 csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
970 csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
971 // Trigger an illegal instr exception when:
972 // * unimplemented csr is being read/written
973 // * csr access is illegal
974 csrExceptionVec(illegalInstr) := isIllegalAddr || isIllegalAccess || isIllegalPrivOp
1101 io.out.bits.ctrl.exceptionVec.get := csrExceptionVec
975 cfOut.exceptionVec := csrExceptionVec
1102
1103 XSDebug(io.in.valid && isEbreak, s"Debug Mode: an Ebreak is executed, ebreak cause exception ? ${ebreakCauseException}\n")
1104
1105 /**
1106 * Exception and Intr
1107 */
1108 val ideleg = (mideleg & mip.asUInt)
1109 def priviledgedEnableDetect(x: Bool): Bool = Mux(x, ((priviledgeMode === ModeS) && mstatusStruct.ie.s) || (priviledgeMode < ModeS),

--- 17 unchanged lines hidden (view full) ---

1127 mipWire.s.m := csrio.externalInterrupt.msip
1128 mipWire.e.m := csrio.externalInterrupt.meip
1129 mipWire.e.s := csrio.externalInterrupt.seip
1130
1131 // interrupts
1132 val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))
1133 val raiseIntr = csrio.exception.valid && csrio.exception.bits.isInterrupt
1134 val ivmEnable = tlbBundle.priv.imode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
976
977 XSDebug(io.in.valid && isEbreak, s"Debug Mode: an Ebreak is executed, ebreak cause exception ? ${ebreakCauseException}\n")
978
979 /**
980 * Exception and Intr
981 */
982 val ideleg = (mideleg & mip.asUInt)
983 def priviledgedEnableDetect(x: Bool): Bool = Mux(x, ((priviledgeMode === ModeS) && mstatusStruct.ie.s) || (priviledgeMode < ModeS),

--- 17 unchanged lines hidden (view full) ---

1001 mipWire.s.m := csrio.externalInterrupt.msip
1002 mipWire.e.m := csrio.externalInterrupt.meip
1003 mipWire.e.s := csrio.externalInterrupt.seip
1004
1005 // interrupts
1006 val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))
1007 val raiseIntr = csrio.exception.valid && csrio.exception.bits.isInterrupt
1008 val ivmEnable = tlbBundle.priv.imode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1135 val iexceptionPC = Mux(ivmEnable, SignExt(csrio.exception.bits.pc, XLEN), csrio.exception.bits.pc)
1009 val iexceptionPC = Mux(ivmEnable, SignExt(csrio.exception.bits.uop.cf.pc, XLEN), csrio.exception.bits.uop.cf.pc)
1136 val dvmEnable = tlbBundle.priv.dmode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1010 val dvmEnable = tlbBundle.priv.dmode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1137 val dexceptionPC = Mux(dvmEnable, SignExt(csrio.exception.bits.pc, XLEN), csrio.exception.bits.pc)
1011 val dexceptionPC = Mux(dvmEnable, SignExt(csrio.exception.bits.uop.cf.pc, XLEN), csrio.exception.bits.uop.cf.pc)
1138 XSDebug(raiseIntr, "interrupt: pc=0x%x, %d\n", dexceptionPC, intrNO)
1139 val raiseDebugIntr = intrNO === IRQ_DEBUG.U && raiseIntr
1140
1141 // exceptions
1142 val raiseException = csrio.exception.valid && !csrio.exception.bits.isInterrupt
1012 XSDebug(raiseIntr, "interrupt: pc=0x%x, %d\n", dexceptionPC, intrNO)
1013 val raiseDebugIntr = intrNO === IRQ_DEBUG.U && raiseIntr
1014
1015 // exceptions
1016 val raiseException = csrio.exception.valid && !csrio.exception.bits.isInterrupt
1143 val hasInstrPageFault = csrio.exception.bits.exceptionVec(instrPageFault) && raiseException
1144 val hasLoadPageFault = csrio.exception.bits.exceptionVec(loadPageFault) && raiseException
1145 val hasStorePageFault = csrio.exception.bits.exceptionVec(storePageFault) && raiseException
1146 val hasStoreAddrMisaligned = csrio.exception.bits.exceptionVec(storeAddrMisaligned) && raiseException
1147 val hasLoadAddrMisaligned = csrio.exception.bits.exceptionVec(loadAddrMisaligned) && raiseException
1148 val hasInstrAccessFault = csrio.exception.bits.exceptionVec(instrAccessFault) && raiseException
1149 val hasLoadAccessFault = csrio.exception.bits.exceptionVec(loadAccessFault) && raiseException
1150 val hasStoreAccessFault = csrio.exception.bits.exceptionVec(storeAccessFault) && raiseException
1151 val hasbreakPoint = csrio.exception.bits.exceptionVec(breakPoint) && raiseException
1152 val hasSingleStep = csrio.exception.bits.singleStep && raiseException
1153// val hasTriggerHit = (csrio.exception.bits.trigger.hit) && raiseException
1017 val hasInstrPageFault = csrio.exception.bits.uop.cf.exceptionVec(instrPageFault) && raiseException
1018 val hasLoadPageFault = csrio.exception.bits.uop.cf.exceptionVec(loadPageFault) && raiseException
1019 val hasStorePageFault = csrio.exception.bits.uop.cf.exceptionVec(storePageFault) && raiseException
1020 val hasStoreAddrMisaligned = csrio.exception.bits.uop.cf.exceptionVec(storeAddrMisaligned) && raiseException
1021 val hasLoadAddrMisaligned = csrio.exception.bits.uop.cf.exceptionVec(loadAddrMisaligned) && raiseException
1022 val hasInstrAccessFault = csrio.exception.bits.uop.cf.exceptionVec(instrAccessFault) && raiseException
1023 val hasLoadAccessFault = csrio.exception.bits.uop.cf.exceptionVec(loadAccessFault) && raiseException
1024 val hasStoreAccessFault = csrio.exception.bits.uop.cf.exceptionVec(storeAccessFault) && raiseException
1025 val hasbreakPoint = csrio.exception.bits.uop.cf.exceptionVec(breakPoint) && raiseException
1026 val hasSingleStep = csrio.exception.bits.uop.ctrl.singleStep && raiseException
1027 val hasTriggerHit = (csrio.exception.bits.uop.cf.trigger.hit) && raiseException
1154
1155 XSDebug(hasSingleStep, "Debug Mode: single step exception\n")
1028
1029 XSDebug(hasSingleStep, "Debug Mode: single step exception\n")
1156// XSDebug(hasTriggerHit, p"Debug Mode: trigger hit, is frontend? ${Binary(csrio.exception.bits.trigger.frontendHit.asUInt)} " +
1157// p"backend hit vec ${Binary(csrio.exception.bits.trigger.backendHit.asUInt)}\n")
1030 XSDebug(hasTriggerHit, p"Debug Mode: trigger hit, is frontend? ${Binary(csrio.exception.bits.uop.cf.trigger.frontendHit.asUInt)} " +
1031 p"backend hit vec ${Binary(csrio.exception.bits.uop.cf.trigger.backendHit.asUInt)}\n")
1158
1032
1159 val raiseExceptionVec = csrio.exception.bits.exceptionVec
1033 val raiseExceptionVec = csrio.exception.bits.uop.cf.exceptionVec
1160 val regularExceptionNO = ExceptionNO.priorities.foldRight(0.U)((i: Int, sum: UInt) => Mux(raiseExceptionVec(i), i.U, sum))
1034 val regularExceptionNO = ExceptionNO.priorities.foldRight(0.U)((i: Int, sum: UInt) => Mux(raiseExceptionVec(i), i.U, sum))
1161 val exceptionNO = Mux(hasSingleStep, 3.U, regularExceptionNO) // Todo: Trigger
1035 val exceptionNO = Mux(hasSingleStep || hasTriggerHit, 3.U, regularExceptionNO)
1162 val causeNO = (raiseIntr << (XLEN-1)).asUInt | Mux(raiseIntr, intrNO, exceptionNO)
1163
1164 val raiseExceptionIntr = csrio.exception.valid
1165
1036 val causeNO = (raiseIntr << (XLEN-1)).asUInt | Mux(raiseIntr, intrNO, exceptionNO)
1037
1038 val raiseExceptionIntr = csrio.exception.valid
1039
1166 val raiseDebugExceptionIntr = !debugMode && (hasbreakPoint || raiseDebugIntr || hasSingleStep) // TODO
1040 val raiseDebugExceptionIntr = !debugMode && (hasbreakPoint || raiseDebugIntr || hasSingleStep || hasTriggerHit && triggerAction) // TODO
1167 val ebreakEnterParkLoop = debugMode && raiseExceptionIntr
1168
1169 XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",
1170 dexceptionPC, intrNO, intrVec, exceptionNO, raiseExceptionVec.asUInt
1171 )
1172 XSDebug(raiseExceptionIntr,
1173 "pc %x mstatus %x mideleg %x medeleg %x mode %x\n",
1174 dexceptionPC,

--- 15 unchanged lines hidden (view full) ---

1190 hasStoreAccessFault,
1191 hasLoadAddrMisaligned,
1192 hasStoreAddrMisaligned
1193 )).asUInt.orR
1194 when (RegNext(RegNext(updateTval))) {
1195 val tval = Mux(
1196 RegNext(RegNext(hasInstrPageFault || hasInstrAccessFault)),
1197 RegNext(RegNext(Mux(
1041 val ebreakEnterParkLoop = debugMode && raiseExceptionIntr
1042
1043 XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",
1044 dexceptionPC, intrNO, intrVec, exceptionNO, raiseExceptionVec.asUInt
1045 )
1046 XSDebug(raiseExceptionIntr,
1047 "pc %x mstatus %x mideleg %x medeleg %x mode %x\n",
1048 dexceptionPC,

--- 15 unchanged lines hidden (view full) ---

1064 hasStoreAccessFault,
1065 hasLoadAddrMisaligned,
1066 hasStoreAddrMisaligned
1067 )).asUInt.orR
1068 when (RegNext(RegNext(updateTval))) {
1069 val tval = Mux(
1070 RegNext(RegNext(hasInstrPageFault || hasInstrAccessFault)),
1071 RegNext(RegNext(Mux(
1198 csrio.exception.bits.crossPageIPFFix,
1199 SignExt(csrio.exception.bits.pc + 2.U, XLEN),
1072 csrio.exception.bits.uop.cf.crossPageIPFFix,
1073 SignExt(csrio.exception.bits.uop.cf.pc + 2.U, XLEN),
1200 iexceptionPC
1201 ))),
1202 memExceptionAddr
1203 )
1204 when (RegNext(priviledgeMode === ModeM)) {
1205 mtval := tval
1206 }.otherwise {
1207 stval := tval

--- 4 unchanged lines hidden (view full) ---

1212 val deleg = Mux(raiseIntr, mideleg , medeleg)
1213 // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
1214 val delegS = deleg(causeNO(3,0)) && (priviledgeMode < ModeM)
1215 val clearTval = !updateTval || raiseIntr
1216 val isXRet = io.in.valid && func === CSROpType.jmp && !isEcall && !isEbreak
1217
1218 // ctrl block will use theses later for flush
1219 val isXRetFlag = RegInit(false.B)
1074 iexceptionPC
1075 ))),
1076 memExceptionAddr
1077 )
1078 when (RegNext(priviledgeMode === ModeM)) {
1079 mtval := tval
1080 }.otherwise {
1081 stval := tval

--- 4 unchanged lines hidden (view full) ---

1086 val deleg = Mux(raiseIntr, mideleg , medeleg)
1087 // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
1088 val delegS = deleg(causeNO(3,0)) && (priviledgeMode < ModeM)
1089 val clearTval = !updateTval || raiseIntr
1090 val isXRet = io.in.valid && func === CSROpType.jmp && !isEcall && !isEbreak
1091
1092 // ctrl block will use theses later for flush
1093 val isXRetFlag = RegInit(false.B)
1220 when (DelayN(io.flush.valid, 5)) {
1094 when (DelayN(io.redirectIn.valid, 5)) {
1221 isXRetFlag := false.B
1222 }.elsewhen (isXRet) {
1223 isXRetFlag := true.B
1224 }
1225 csrio.isXRet := isXRetFlag
1226 val retTargetReg = RegEnable(retTarget, isXRet)
1227
1228 val tvec = Mux(delegS, stvec, mtvec)

--- 25 unchanged lines hidden (view full) ---

1254 dcsrNew.cause := 3.U
1255 dcsrNew.prv := priviledgeMode
1256 priviledgeMode := ModeM
1257 XSDebug(raiseDebugIntr, "Debug Mode: Trap to %x at pc %x\n", debugTrapTarget, dpc)
1258 }.elsewhen ((hasbreakPoint || hasSingleStep) && !debugMode) {
1259 // ebreak or ss in running hart
1260 debugModeNew := true.B
1261 dpc := iexceptionPC
1095 isXRetFlag := false.B
1096 }.elsewhen (isXRet) {
1097 isXRetFlag := true.B
1098 }
1099 csrio.isXRet := isXRetFlag
1100 val retTargetReg = RegEnable(retTarget, isXRet)
1101
1102 val tvec = Mux(delegS, stvec, mtvec)

--- 25 unchanged lines hidden (view full) ---

1128 dcsrNew.cause := 3.U
1129 dcsrNew.prv := priviledgeMode
1130 priviledgeMode := ModeM
1131 XSDebug(raiseDebugIntr, "Debug Mode: Trap to %x at pc %x\n", debugTrapTarget, dpc)
1132 }.elsewhen ((hasbreakPoint || hasSingleStep) && !debugMode) {
1133 // ebreak or ss in running hart
1134 debugModeNew := true.B
1135 dpc := iexceptionPC
1262 dcsrNew.cause := 0.U // Todo
1136 dcsrNew.cause := Mux(hasTriggerHit, 2.U, Mux(hasbreakPoint, 1.U, 4.U))
1263 dcsrNew.prv := priviledgeMode // TODO
1264 priviledgeMode := ModeM
1265 mstatusNew.mprv := false.B
1266 }
1267 dcsr := dcsrNew.asUInt
1268 debugIntrEnable := false.B
1269 }.elsewhen (debugMode) {
1270 //do nothing

--- 13 unchanged lines hidden (view full) ---

1284 mstatusNew.ie.m := false.B
1285 priviledgeMode := ModeM
1286 when (clearTval) { mtval := 0.U }
1287 }
1288 mstatus := mstatusNew.asUInt
1289 debugMode := debugModeNew
1290 }
1291
1137 dcsrNew.prv := priviledgeMode // TODO
1138 priviledgeMode := ModeM
1139 mstatusNew.mprv := false.B
1140 }
1141 dcsr := dcsrNew.asUInt
1142 debugIntrEnable := false.B
1143 }.elsewhen (debugMode) {
1144 //do nothing

--- 13 unchanged lines hidden (view full) ---

1158 mstatusNew.ie.m := false.B
1159 priviledgeMode := ModeM
1160 when (clearTval) { mtval := 0.U }
1161 }
1162 mstatus := mstatusNew.asUInt
1163 debugMode := debugModeNew
1164 }
1165
1292 XSDebug(raiseExceptionIntr && delegS, "sepc is written!!! pc:%x\n", io.in.bits.data.pc.get)
1166 XSDebug(raiseExceptionIntr && delegS, "sepc is written!!! pc:%x\n", cfIn.pc)
1293
1294 // Distributed CSR update req
1295 //
1296 // For now we use it to implement customized cache op
1297 // It can be delayed if necessary
1298
1299 val delayedUpdate0 = DelayN(csrio.distributedUpdate(0), 2)
1300 val delayedUpdate1 = DelayN(csrio.distributedUpdate(1), 2)

--- 32 unchanged lines hidden (view full) ---

1333 }
1334
1335 def readWithScala(addr: Int): UInt = mapping(addr)._1
1336
1337 val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
1338
1339 // Always instantiate basic difftest modules.
1340 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1167
1168 // Distributed CSR update req
1169 //
1170 // For now we use it to implement customized cache op
1171 // It can be delayed if necessary
1172
1173 val delayedUpdate0 = DelayN(csrio.distributedUpdate(0), 2)
1174 val delayedUpdate1 = DelayN(csrio.distributedUpdate(1), 2)

--- 32 unchanged lines hidden (view full) ---

1207 }
1208
1209 def readWithScala(addr: Int): UInt = mapping(addr)._1
1210
1211 val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
1212
1213 // Always instantiate basic difftest modules.
1214 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1341 val difftest = Module(new DifftestArchEvent)
1342 difftest.io.clock := clock
1343 difftest.io.coreid := csrio.hartId
1344 difftest.io.intrNO := RegNext(RegNext(RegNext(difftestIntrNO)))
1345 difftest.io.cause := RegNext(RegNext(RegNext(Mux(csrio.exception.valid, causeNO, 0.U))))
1346 difftest.io.exceptionPC := RegNext(RegNext(RegNext(dexceptionPC)))
1215 val difftest = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true)
1216 difftest.clock := clock
1217 difftest.coreid := csrio.hartId
1218 difftest.valid := csrio.exception.valid
1219 difftest.interrupt := Mux(raiseIntr, causeNO, 0.U)
1220 difftest.exception := Mux(raiseException, causeNO, 0.U)
1221 difftest.exceptionPC := dexceptionPC
1347 if (env.EnableDifftest) {
1222 if (env.EnableDifftest) {
1348 difftest.io.exceptionInst := RegNext(RegNext(RegNext(csrio.exception.bits.instr)))
1223 difftest.exceptionInst := csrio.exception.bits.uop.cf.instr
1349 }
1350 }
1351
1352 // Always instantiate basic difftest modules.
1353 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1224 }
1225 }
1226
1227 // Always instantiate basic difftest modules.
1228 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1354 val difftest = Module(new DifftestCSRState)
1355 difftest.io.clock := clock
1356 difftest.io.coreid := csrio.hartId
1357 difftest.io.priviledgeMode := priviledgeMode
1358 difftest.io.mstatus := mstatus
1359 difftest.io.sstatus := mstatus & sstatusRmask
1360 difftest.io.mepc := mepc
1361 difftest.io.sepc := sepc
1362 difftest.io.mtval:= mtval
1363 difftest.io.stval:= stval
1364 difftest.io.mtvec := mtvec
1365 difftest.io.stvec := stvec
1366 difftest.io.mcause := mcause
1367 difftest.io.scause := scause
1368 difftest.io.satp := satp
1369 difftest.io.mip := mipReg
1370 difftest.io.mie := mie
1371 difftest.io.mscratch := mscratch
1372 difftest.io.sscratch := sscratch
1373 difftest.io.mideleg := mideleg
1374 difftest.io.medeleg := medeleg
1229 val difftest = DifftestModule(new DiffCSRState)
1230 difftest.clock := clock
1231 difftest.coreid := csrio.hartId
1232 difftest.priviledgeMode := priviledgeMode
1233 difftest.mstatus := mstatus
1234 difftest.sstatus := mstatus & sstatusRmask
1235 difftest.mepc := mepc
1236 difftest.sepc := sepc
1237 difftest.mtval:= mtval
1238 difftest.stval:= stval
1239 difftest.mtvec := mtvec
1240 difftest.stvec := stvec
1241 difftest.mcause := mcause
1242 difftest.scause := scause
1243 difftest.satp := satp
1244 difftest.mip := mipReg
1245 difftest.mie := mie
1246 difftest.mscratch := mscratch
1247 difftest.sscratch := sscratch
1248 difftest.mideleg := mideleg
1249 difftest.medeleg := medeleg
1375 }
1376
1377 if(env.AlwaysBasicDiff || env.EnableDifftest) {
1250 }
1251
1252 if(env.AlwaysBasicDiff || env.EnableDifftest) {
1378 val difftest = Module(new DifftestDebugMode)
1379 difftest.io.clock := clock
1380 difftest.io.coreid := csrio.hartId
1381 difftest.io.debugMode := debugMode
1382 difftest.io.dcsr := dcsr
1383 difftest.io.dpc := dpc
1384 difftest.io.dscratch0 := dscratch
1385 difftest.io.dscratch1 := dscratch1
1253 val difftest = DifftestModule(new DiffDebugMode)
1254 difftest.clock := clock
1255 difftest.coreid := csrio.hartId
1256 difftest.debugMode := debugMode
1257 difftest.dcsr := dcsr
1258 difftest.dpc := dpc
1259 difftest.dscratch0 := dscratch
1260 difftest.dscratch1 := dscratch1
1386 }
1261 }
1387
1388 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1389 val difftest = Module(new DifftestVectorState)
1390 difftest.io.clock := clock
1391 difftest.io.coreid := csrio.hartId
1392 difftest.io.vstart := vstart
1393 difftest.io.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
1394 difftest.io.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
1395 difftest.io.vcsr := vcsr
1396 difftest.io.vl := vl
1397 difftest.io.vtype := vtype
1398 difftest.io.vlenb := vlenb
1399 }
1400}
1401
1402class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst {
1403 val io = IO(new Bundle {
1404 val distribute_csr = Flipped(new DistributedCSRIO())
1405 val hpmevent = Output(Vec(29, UInt(XLEN.W)))
1406 })
1407

--- 19 unchanged lines hidden --- 		1262}
1263
1264class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst {
1265 val io = IO(new Bundle {
1266 val distribute_csr = Flipped(new DistributedCSRIO())
1267 val hpmevent = Output(Vec(29, UInt(XLEN.W)))
1268 })
1269

--- 19 unchanged lines hidden ---