CSR.scala (560b69b7b31bb98449354526dc9c8ed49eeedb10) CSR.scala (45f43e6e5f88874a7573ff096d1e5c2855bd16c7)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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23import freechips.rocketchip.util._
24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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23import freechips.rocketchip.util._
24import utility.MaskedRegMap.WritableMask
25import utils._
26import utility._
27import xiangshan.ExceptionNO._
28import xiangshan._
29import xiangshan.backend.fu.util._
30import xiangshan.cache._
31import xiangshan.backend.Bundles.ExceptionInfo
32import xiangshan.backend.fu.util.CSR.CSRNamedConstant.ContextStatus
33import utils.MathUtils.{BigIntGenMask, BigIntNot}
34
35// Trigger Tdata1 bundles
36trait HasTriggerConst {
37 def I_Trigger = 0.U
38 def S_Trigger = 1.U
39 def L_Trigger = 2.U
40 def GenESL(triggerType: UInt) = Cat((triggerType === I_Trigger), (triggerType === S_Trigger), (triggerType === L_Trigger))
41}
42
31
32// Trigger Tdata1 bundles
33trait HasTriggerConst {
34 def I_Trigger = 0.U
35 def S_Trigger = 1.U
36 def L_Trigger = 2.U
37 def GenESL(triggerType: UInt) = Cat((triggerType === I_Trigger), (triggerType === S_Trigger), (triggerType === L_Trigger))
38}
39
40class TdataBundle extends Bundle {
41 val ttype = UInt(4.W)
42 val dmode = Bool()
43 val maskmax = UInt(6.W)
44 val zero1 = UInt(30.W)
45 val sizehi = UInt(2.W)
46 val hit = Bool()
47 val select = Bool()
48 val timing = Bool()
49 val sizelo = UInt(2.W)
50 val action = UInt(4.W)
51 val chain = Bool()
52 val matchType = UInt(4.W)
53 val m = Bool()
54 val zero2 = Bool()
55 val s = Bool()
56 val u = Bool()
57 val execute = Bool()
58 val store = Bool()
59 val load = Bool()
60}
61
43class FpuCsrIO extends Bundle {
44 val fflags = Output(Valid(UInt(5.W)))
45 val isIllegal = Output(Bool())
46 val dirty_fs = Output(Bool())
47 val frm = Input(UInt(3.W))
48}
49
62class FpuCsrIO extends Bundle {
63 val fflags = Output(Valid(UInt(5.W)))
64 val isIllegal = Output(Bool())
65 val dirty_fs = Output(Bool())
66 val frm = Input(UInt(3.W))
67}
68
50class VpuCsrIO(implicit p: Parameters) extends XSBundle {
51 val vstart = Input(UInt(XLEN.W))
52 val vxsat = Input(UInt(1.W))
53 val vxrm = Input(UInt(2.W))
54 val vcsr = Input(UInt(XLEN.W))
55 val vl = Input(UInt(XLEN.W))
56 val vtype = Input(UInt(XLEN.W))
57 val vlenb = Input(UInt(XLEN.W))
58
69
59 val vill = Input(UInt(1.W))
60 val vma = Input(UInt(1.W))
61 val vta = Input(UInt(1.W))
62 val vsew = Input(UInt(3.W))
63 val vlmul = Input(UInt(3.W))
64
65 val set_vstart = Output(Valid(UInt(XLEN.W)))
66 val set_vl = Output(Valid(UInt(XLEN.W)))
67 val set_vtype = Output(Valid(UInt(XLEN.W)))
68 val set_vxsat = Output(Valid(UInt(1.W)))
69
70 val dirty_vs = Output(Bool())
71}
72
73
74class PerfCounterIO(implicit p: Parameters) extends XSBundle {
75 val perfEventsFrontend = Vec(numCSRPCntFrontend, new PerfEvent)
76 val perfEventsCtrl = Vec(numCSRPCntCtrl, new PerfEvent)
77 val perfEventsLsu = Vec(numCSRPCntLsu, new PerfEvent)
78 val perfEventsHc = Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)
79 val retiredInstr = UInt(3.W)
80 val frontendInfo = new Bundle {
81 val ibufFull = Bool()

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90 val fpdqFull = Bool()
91 val lsdqFull = Bool()
92 }
93 val memInfo = new Bundle {
94 val sqFull = Bool()
95 val lqFull = Bool()
96 val dcacheMSHRFull = Bool()
97 }
70class PerfCounterIO(implicit p: Parameters) extends XSBundle {
71 val perfEventsFrontend = Vec(numCSRPCntFrontend, new PerfEvent)
72 val perfEventsCtrl = Vec(numCSRPCntCtrl, new PerfEvent)
73 val perfEventsLsu = Vec(numCSRPCntLsu, new PerfEvent)
74 val perfEventsHc = Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)
75 val retiredInstr = UInt(3.W)
76 val frontendInfo = new Bundle {
77 val ibufFull = Bool()

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86 val fpdqFull = Bool()
87 val lsdqFull = Bool()
88 }
89 val memInfo = new Bundle {
90 val sqFull = Bool()
91 val lqFull = Bool()
92 val dcacheMSHRFull = Bool()
93 }
94
95 val cacheInfo = new Bundle {
96 val l2MSHRFull = Bool()
97 val l3MSHRFull = Bool()
98 val l2nAcquire = UInt(XLEN.W)
99 val l2nAcquireMiss = UInt(XLEN.W)
100 val l3nAcquire = UInt(XLEN.W)
101 val l3nAcquireMiss = UInt(XLEN.W)
102 }
98}
99
100class CSRFileIO(implicit p: Parameters) extends XSBundle {
101 val hartId = Input(UInt(8.W))
102 // output (for func === CSROpType.jmp)
103 val perf = Input(new PerfCounterIO)
104 val isPerfCnt = Output(Bool())
105 // to FPU
106 val fpu = Flipped(new FpuCsrIO)
103}
104
105class CSRFileIO(implicit p: Parameters) extends XSBundle {
106 val hartId = Input(UInt(8.W))
107 // output (for func === CSROpType.jmp)
108 val perf = Input(new PerfCounterIO)
109 val isPerfCnt = Output(Bool())
110 // to FPU
111 val fpu = Flipped(new FpuCsrIO)
107 // to VPU
108 val vpu = Flipped(new VpuCsrIO)
109 // from rob
110 val exception = Flipped(ValidIO(new ExceptionInfo))
111 // to ROB
112 val isXRet = Output(Bool())
113 val trapTarget = Output(UInt(VAddrBits.W))
114 val interrupt = Output(Bool())
115 val wfi_event = Output(Bool())
116 // from LSQ

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125 // to Fence to disable sfence
126 val disableSfence = Output(Bool())
127 // Custom microarchiture ctrl signal
128 val customCtrl = Output(new CustomCSRCtrlIO)
129 // distributed csr write
130 val distributedUpdate = Vec(2, Flipped(new DistributedCSRUpdateReq))
131}
132
112 // from rob
113 val exception = Flipped(ValidIO(new ExceptionInfo))
114 // to ROB
115 val isXRet = Output(Bool())
116 val trapTarget = Output(UInt(VAddrBits.W))
117 val interrupt = Output(Bool())
118 val wfi_event = Output(Bool())
119 // from LSQ

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128 // to Fence to disable sfence
129 val disableSfence = Output(Bool())
130 // Custom microarchiture ctrl signal
131 val customCtrl = Output(new CustomCSRCtrlIO)
132 // distributed csr write
133 val distributedUpdate = Vec(2, Flipped(new DistributedCSRUpdateReq))
134}
135
133class VtypeStruct(implicit p: Parameters) extends XSBundle {
134 val vill = UInt(1.W)
135 val reserved = UInt((XLEN - 9).W)
136 val vma = UInt(1.W)
137 val vta = UInt(1.W)
138 val vsew = UInt(3.W)
139 val vlmul = UInt(3.W)
140}
141
142class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
143 with HasCSRConst
144 with PMPMethod
145 with PMAMethod
146 with HasTriggerConst
147 with HasXSParameter
148 with SdtrigExt
149 with DebugCSR
136class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMPMethod with PMAMethod with HasTriggerConst
150{
137{
151 val csrio = io.csrio.get
138 val csrio = IO(new CSRFileIO)
152
139
140 val cfIn = io.in.bits.uop.cf
141 val cfOut = Wire(new CtrlFlow)
142 cfOut := cfIn
153 val flushPipe = Wire(Bool())
154
155 val (valid, src1, src2, func) = (
156 io.in.valid,
143 val flushPipe = Wire(Bool())
144
145 val (valid, src1, src2, func) = (
146 io.in.valid,
157 io.in.bits.data.src(0),
158 io.in.bits.data.imm,
159 io.in.bits.ctrl.fuOpType
147 io.in.bits.src(0),
148 io.in.bits.uop.ctrl.imm,
149 io.in.bits.uop.ctrl.fuOpType
160 )
161
162 // CSR define
163
164 class Priv extends Bundle {
165 val m = Output(Bool())
166 val h = Output(Bool())
167 val s = Output(Bool())
168 val u = Output(Bool())
169 }
170
150 )
151
152 // CSR define
153
154 class Priv extends Bundle {
155 val m = Output(Bool())
156 val h = Output(Bool())
157 val s = Output(Bool())
158 val u = Output(Bool())
159 }
160
161 val csrNotImplemented = RegInit(UInt(XLEN.W), 0.U)
162
163 class DcsrStruct extends Bundle {
164 val xdebugver = Output(UInt(2.W))
165 val zero4 = Output(UInt(2.W))
166 val zero3 = Output(UInt(12.W))
167 val ebreakm = Output(Bool())
168 val ebreakh = Output(Bool())
169 val ebreaks = Output(Bool())
170 val ebreaku = Output(Bool())
171 val stepie = Output(Bool()) // 0
172 val stopcycle = Output(Bool())
173 val stoptime = Output(Bool())
174 val cause = Output(UInt(3.W))
175 val v = Output(Bool()) // 0
176 val mprven = Output(Bool())
177 val nmip = Output(Bool())
178 val step = Output(Bool())
179 val prv = Output(UInt(2.W))
180 }
181
171 class MstatusStruct extends Bundle {
172 val sd = Output(UInt(1.W))
173
174 val pad1 = if (XLEN == 64) Output(UInt(25.W)) else null
175 val mbe = if (XLEN == 64) Output(UInt(1.W)) else null
176 val sbe = if (XLEN == 64) Output(UInt(1.W)) else null
177 val sxl = if (XLEN == 64) Output(UInt(2.W)) else null
178 val uxl = if (XLEN == 64) Output(UInt(2.W)) else null
179 val pad0 = if (XLEN == 64) Output(UInt(9.W)) else Output(UInt(8.W))
180
181 val tsr = Output(UInt(1.W))
182 val tw = Output(UInt(1.W))
183 val tvm = Output(UInt(1.W))
184 val mxr = Output(UInt(1.W))
185 val sum = Output(UInt(1.W))
186 val mprv = Output(UInt(1.W))
187 val xs = Output(UInt(2.W))
188 val fs = Output(UInt(2.W))
189 val mpp = Output(UInt(2.W))
182 class MstatusStruct extends Bundle {
183 val sd = Output(UInt(1.W))
184
185 val pad1 = if (XLEN == 64) Output(UInt(25.W)) else null
186 val mbe = if (XLEN == 64) Output(UInt(1.W)) else null
187 val sbe = if (XLEN == 64) Output(UInt(1.W)) else null
188 val sxl = if (XLEN == 64) Output(UInt(2.W)) else null
189 val uxl = if (XLEN == 64) Output(UInt(2.W)) else null
190 val pad0 = if (XLEN == 64) Output(UInt(9.W)) else Output(UInt(8.W))
191
192 val tsr = Output(UInt(1.W))
193 val tw = Output(UInt(1.W))
194 val tvm = Output(UInt(1.W))
195 val mxr = Output(UInt(1.W))
196 val sum = Output(UInt(1.W))
197 val mprv = Output(UInt(1.W))
198 val xs = Output(UInt(2.W))
199 val fs = Output(UInt(2.W))
200 val mpp = Output(UInt(2.W))
190 val vs = Output(UInt(2.W))
201 val hpp = Output(UInt(2.W))
191 val spp = Output(UInt(1.W))
192 val pie = new Priv
193 val ie = new Priv
194 assert(this.getWidth == XLEN)
195
196 def ube = pie.h // a little ugly
197 def ube_(r: UInt): Unit = {
198 pie.h := r(0)
199 }
200 }
201
202 class Interrupt extends Bundle {
203// val d = Output(Bool()) // Debug
204 val e = new Priv
205 val t = new Priv
206 val s = new Priv
207 }
208
202 val spp = Output(UInt(1.W))
203 val pie = new Priv
204 val ie = new Priv
205 assert(this.getWidth == XLEN)
206
207 def ube = pie.h // a little ugly
208 def ube_(r: UInt): Unit = {
209 pie.h := r(0)
210 }
211 }
212
213 class Interrupt extends Bundle {
214// val d = Output(Bool()) // Debug
215 val e = new Priv
216 val t = new Priv
217 val s = new Priv
218 }
219
209 val csrNotImplemented = RegInit(UInt(XLEN.W), 0.U)
210
211 // Debug CSRs
220 // Debug CSRs
212 val dcsr = RegInit(UInt(32.W), DcsrStruct.init)
221 val dcsr = RegInit(UInt(32.W), 0x4000b000.U)
213 val dpc = Reg(UInt(64.W))
222 val dpc = Reg(UInt(64.W))
214 val dscratch0 = Reg(UInt(64.W))
223 val dscratch = Reg(UInt(64.W))
215 val dscratch1 = Reg(UInt(64.W))
216 val debugMode = RegInit(false.B)
224 val dscratch1 = Reg(UInt(64.W))
225 val debugMode = RegInit(false.B)
217 val debugIntrEnable = RegInit(true.B) // debug interrupt will be handle only when debugIntrEnable
226 val debugIntrEnable = RegInit(true.B)
218 csrio.debugMode := debugMode
219
220 val dpcPrev = RegNext(dpc)
221 XSDebug(dpcPrev =/= dpc, "Debug Mode: dpc is altered! Current is %x, previous is %x\n", dpc, dpcPrev)
222
227 csrio.debugMode := debugMode
228
229 val dpcPrev = RegNext(dpc)
230 XSDebug(dpcPrev =/= dpc, "Debug Mode: dpc is altered! Current is %x, previous is %x\n", dpc, dpcPrev)
231
232 // dcsr value table
233 // | debugver | 0100
234 // | zero | 10 bits of 0
235 // | ebreakvs | 0
236 // | ebreakvu | 0
237 // | ebreakm | 1 if ebreak enters debug
238 // | zero | 0
239 // | ebreaks |
240 // | ebreaku |
241 // | stepie | disable interrupts in singlestep
242 // | stopcount| stop counter, 0
243 // | stoptime | stop time, 0
244 // | cause | 3 bits read only
245 // | v | 0
246 // | mprven | 1
247 // | nmip | read only
248 // | step |
249 // | prv | 2 bits
250
223 val dcsrData = Wire(new DcsrStruct)
224 dcsrData := dcsr.asTypeOf(new DcsrStruct)
225 val dcsrMask = ZeroExt(GenMask(15) | GenMask(13, 11) | GenMask(4) | GenMask(2, 0), XLEN)// Dcsr write mask
226 def dcsrUpdateSideEffect(dcsr: UInt): UInt = {
227 val dcsrOld = WireInit(dcsr.asTypeOf(new DcsrStruct))
228 val dcsrNew = dcsr | (dcsrOld.prv(0) | dcsrOld.prv(1)).asUInt // turn 10 priv into 11
229 dcsrNew
230 }
231 // csrio.singleStep := dcsrData.step
232 csrio.customCtrl.singlestep := dcsrData.step && !debugMode
233
234 // Trigger CSRs
251 val dcsrData = Wire(new DcsrStruct)
252 dcsrData := dcsr.asTypeOf(new DcsrStruct)
253 val dcsrMask = ZeroExt(GenMask(15) | GenMask(13, 11) | GenMask(4) | GenMask(2, 0), XLEN)// Dcsr write mask
254 def dcsrUpdateSideEffect(dcsr: UInt): UInt = {
255 val dcsrOld = WireInit(dcsr.asTypeOf(new DcsrStruct))
256 val dcsrNew = dcsr | (dcsrOld.prv(0) | dcsrOld.prv(1)).asUInt // turn 10 priv into 11
257 dcsrNew
258 }
259 // csrio.singleStep := dcsrData.step
260 csrio.customCtrl.singlestep := dcsrData.step && !debugMode
261
262 // Trigger CSRs
235 private val tselectPhy = RegInit(0.U(log2Up(TriggerNum).W))
236
263
237 private val tdata1RegVec = RegInit(VecInit(Seq.fill(TriggerNum)(Tdata1Bundle.default)))
238 private val tdata2RegVec = RegInit(VecInit(Seq.fill(TriggerNum)(0.U(64.W))))
239 private val tdata1WireVec = tdata1RegVec.map(_.asTypeOf(new Tdata1Bundle))
240 private val tdata2WireVec = tdata2RegVec
241 private val tdata1Selected = tdata1RegVec(tselectPhy).asTypeOf(new Tdata1Bundle)
242 private val tdata2Selected = tdata2RegVec(tselectPhy)
243 private val newTriggerChainVec = UIntToOH(tselectPhy, TriggerNum).asBools | tdata1WireVec.map(_.data.asTypeOf(new MControlData).chain)
244 private val newTriggerChainIsLegal = TriggerCheckChainLegal(newTriggerChainVec, TriggerChainMaxLength)
245 val tinfo = RegInit((BigInt(1) << TrigTypeEnum.MCONTROL.litValue.toInt).U(XLEN.W)) // This value should be 4.U
264 val type_config = Array(
265 0.U -> I_Trigger, 1.U -> I_Trigger,
266 2.U -> S_Trigger, 3.U -> S_Trigger,
267 4.U -> L_Trigger, 5.U -> L_Trigger, // No.5 Load Trigger
268 6.U -> I_Trigger, 7.U -> S_Trigger,
269 8.U -> I_Trigger, 9.U -> L_Trigger
270 )
271 def TypeLookup(select: UInt) = MuxLookup(select, I_Trigger)(type_config)
246
272
273 val tdata1Phy = RegInit(VecInit(List.fill(10) {(2L << 60L).U(64.W)})) // init ttype 2
274 val tdata2Phy = Reg(Vec(10, UInt(64.W)))
275 val tselectPhy = RegInit(0.U(4.W))
276 val tinfo = RegInit(2.U(64.W))
277 val tControlPhy = RegInit(0.U(64.W))
278 val triggerAction = RegInit(false.B)
247
279
280 def ReadTdata1(rdata: UInt) = rdata | Cat(triggerAction, 0.U(12.W)) // fix action
281 def WriteTdata1(wdata: UInt): UInt = {
282 val tdata1 = WireInit(tdata1Phy(tselectPhy).asTypeOf(new TdataBundle))
283 val wdata_wire = WireInit(wdata.asTypeOf(new TdataBundle))
284 val tdata1_new = WireInit(wdata.asTypeOf(new TdataBundle))
285 XSDebug(src2(11, 0) === Tdata1.U && valid && func =/= CSROpType.jmp, p"Debug Mode: tdata1(${tselectPhy})is written, the actual value is ${wdata}\n")
286// tdata1_new.hit := wdata(20)
287 tdata1_new.ttype := tdata1.ttype
288 tdata1_new.dmode := 0.U // Mux(debugMode, wdata_wire.dmode, tdata1.dmode)
289 tdata1_new.maskmax := 0.U
290 tdata1_new.hit := 0.U
291 tdata1_new.select := (TypeLookup(tselectPhy) === I_Trigger) && wdata_wire.select
292 when(wdata_wire.action <= 1.U){
293 triggerAction := tdata1_new.action(0)
294 } .otherwise{
295 tdata1_new.action := tdata1.action
296 }
297 tdata1_new.timing := false.B // hardwire this because we have singlestep
298 tdata1_new.zero1 := 0.U
299 tdata1_new.zero2 := 0.U
300 tdata1_new.chain := !tselectPhy(0) && wdata_wire.chain
301 when(wdata_wire.matchType =/= 0.U && wdata_wire.matchType =/= 2.U && wdata_wire.matchType =/= 3.U) {
302 tdata1_new.matchType := tdata1.matchType
303 }
304 tdata1_new.sizehi := Mux(wdata_wire.select && TypeLookup(tselectPhy) === I_Trigger, 0.U, 1.U)
305 tdata1_new.sizelo:= Mux(wdata_wire.select && TypeLookup(tselectPhy) === I_Trigger, 3.U, 1.U)
306 tdata1_new.execute := TypeLookup(tselectPhy) === I_Trigger
307 tdata1_new.store := TypeLookup(tselectPhy) === S_Trigger
308 tdata1_new.load := TypeLookup(tselectPhy) === L_Trigger
309 tdata1_new.asUInt
310 }
311
248 def WriteTselect(wdata: UInt) = {
312 def WriteTselect(wdata: UInt) = {
249 Mux(wdata < TriggerNum.U, wdata(3, 0), tselectPhy)
313 Mux(wdata < 10.U, wdata(3, 0), tselectPhy)
250 }
251
314 }
315
252 def GenTdataDistribute(tdata1: Tdata1Bundle, tdata2: UInt): MatchTriggerIO = {
316 val tcontrolWriteMask = ZeroExt(GenMask(3) | GenMask(7), XLEN)
317
318
319 def GenTdataDistribute(tdata1: TdataBundle, tdata2: UInt): MatchTriggerIO = {
253 val res = Wire(new MatchTriggerIO)
320 val res = Wire(new MatchTriggerIO)
254 val mcontrol: MControlData = WireInit(tdata1.data.asTypeOf(new MControlData))
255 res.matchType := mcontrol.match_.asUInt
256 res.select := mcontrol.select
257 res.timing := mcontrol.timing
258 res.action := mcontrol.action.asUInt
259 res.chain := mcontrol.chain
260 res.execute := mcontrol.execute
261 res.load := mcontrol.load
262 res.store := mcontrol.store
263 res.tdata2 := tdata2
321 res.matchType := tdata1.matchType
322 res.select := tdata1.select
323 res.timing := tdata1.timing
324 res.action := triggerAction
325 res.chain := tdata1.chain
326 res.tdata2 := tdata2
264 res
265 }
266
327 res
328 }
329
267 csrio.customCtrl.frontend_trigger.tUpdate.bits.addr := tselectPhy
268 csrio.customCtrl.mem_trigger.tUpdate.bits.addr := tselectPhy
269 csrio.customCtrl.frontend_trigger.tUpdate.bits.tdata := GenTdataDistribute(tdata1Selected, tdata2Selected)
270 csrio.customCtrl.mem_trigger.tUpdate.bits.tdata := GenTdataDistribute(tdata1Selected, tdata2Selected)
271
330 csrio.customCtrl.frontend_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U)(Seq(
331 0.U -> 0.U,
332 1.U -> 1.U,
333 6.U -> 2.U,
334 8.U -> 3.U
335 ))
336 csrio.customCtrl.mem_trigger.t.bits.addr := MuxLookup(tselectPhy, 0.U)(Seq(
337 2.U -> 0.U,
338 3.U -> 1.U,
339 4.U -> 2.U,
340 5.U -> 3.U,
341 7.U -> 4.U,
342 9.U -> 5.U
343 ))
344 csrio.customCtrl.frontend_trigger.t.bits.tdata := GenTdataDistribute(tdata1Phy(tselectPhy).asTypeOf(new TdataBundle), tdata2Phy(tselectPhy))
345 csrio.customCtrl.mem_trigger.t.bits.tdata := GenTdataDistribute(tdata1Phy(tselectPhy).asTypeOf(new TdataBundle), tdata2Phy(tselectPhy))
346
272 // Machine-Level CSRs
273 // mtvec: {BASE (WARL), MODE (WARL)} where mode is 0 or 1
274 val mtvecMask = ~(0x2.U(XLEN.W))
275 val mtvec = RegInit(UInt(XLEN.W), 0.U)
276 val mcounteren = RegInit(UInt(XLEN.W), 0.U)
277 val mcause = RegInit(UInt(XLEN.W), 0.U)
278 val mtval = RegInit(UInt(XLEN.W), 0.U)
279 val mepc = Reg(UInt(XLEN.W))

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287 val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
288
289 def getMisaMxl(mxl: BigInt): BigInt = mxl << (XLEN - 2)
290 def getMisaExt(ext: Char): Long = 1 << (ext.toInt - 'a'.toInt)
291 var extList = List('a', 's', 'i', 'u')
292 if (HasMExtension) { extList = extList :+ 'm' }
293 if (HasCExtension) { extList = extList :+ 'c' }
294 if (HasFPU) { extList = extList ++ List('f', 'd') }
347 // Machine-Level CSRs
348 // mtvec: {BASE (WARL), MODE (WARL)} where mode is 0 or 1
349 val mtvecMask = ~(0x2.U(XLEN.W))
350 val mtvec = RegInit(UInt(XLEN.W), 0.U)
351 val mcounteren = RegInit(UInt(XLEN.W), 0.U)
352 val mcause = RegInit(UInt(XLEN.W), 0.U)
353 val mtval = RegInit(UInt(XLEN.W), 0.U)
354 val mepc = Reg(UInt(XLEN.W))

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362 val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
363
364 def getMisaMxl(mxl: BigInt): BigInt = mxl << (XLEN - 2)
365 def getMisaExt(ext: Char): Long = 1 << (ext.toInt - 'a'.toInt)
366 var extList = List('a', 's', 'i', 'u')
367 if (HasMExtension) { extList = extList :+ 'm' }
368 if (HasCExtension) { extList = extList :+ 'c' }
369 if (HasFPU) { extList = extList ++ List('f', 'd') }
295 if (HasVPU) { extList = extList :+ 'v' }
296 val misaInitVal = getMisaMxl(2) | extList.foldLeft(0L)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
297 val misa = RegInit(UInt(XLEN.W), misaInitVal.U)
370 val misaInitVal = getMisaMxl(2) | extList.foldLeft(0L)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
371 val misa = RegInit(UInt(XLEN.W), misaInitVal.U)
298 println(s"[CSR] supported isa ext: $extList")
299
300 // MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
301 // (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
302
303 val mvendorid = RegInit(UInt(XLEN.W), 0.U) // this is a non-commercial implementation
304 val marchid = RegInit(UInt(XLEN.W), 25.U) // architecture id for XiangShan is 25; see https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
305 val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation
306 val mhartid = Reg(UInt(XLEN.W)) // the hardware thread running the code
307 when (RegNext(RegNext(reset.asBool) && !reset.asBool)) {
308 mhartid := csrio.hartId
309 }
310 val mconfigptr = RegInit(UInt(XLEN.W), 0.U) // the read-only pointer pointing to the platform config structure, 0 for not supported.
372
373 // MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
374 // (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
375
376 val mvendorid = RegInit(UInt(XLEN.W), 0.U) // this is a non-commercial implementation
377 val marchid = RegInit(UInt(XLEN.W), 25.U) // architecture id for XiangShan is 25; see https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
378 val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation
379 val mhartid = Reg(UInt(XLEN.W)) // the hardware thread running the code
380 when (RegNext(RegNext(reset.asBool) && !reset.asBool)) {
381 mhartid := csrio.hartId
382 }
383 val mconfigptr = RegInit(UInt(XLEN.W), 0.U) // the read-only pointer pointing to the platform config structure, 0 for not supported.
311 val mstatus = RegInit("ha00002200".U(XLEN.W))
384 val mstatus = RegInit("ha00002000".U(XLEN.W))
312
313 // mstatus Value Table
385
386 // mstatus Value Table
314 // | sd | Read Only
315 // | pad1 | WPRI
387 // | sd |
388 // | pad1 |
316 // | sxl | hardlinked to 10, use 00 to pass xv6 test
317 // | uxl | hardlinked to 10
318 // | pad0 |
319 // | tsr |
320 // | tw |
321 // | tvm |
322 // | mxr |
323 // | sum |
324 // | mprv |
325 // | xs | 00 |
326 // | fs | 01 |
327 // | mpp | 00 |
389 // | sxl | hardlinked to 10, use 00 to pass xv6 test
390 // | uxl | hardlinked to 10
391 // | pad0 |
392 // | tsr |
393 // | tw |
394 // | tvm |
395 // | mxr |
396 // | sum |
397 // | mprv |
398 // | xs | 00 |
399 // | fs | 01 |
400 // | mpp | 00 |
328 // | vs | 01 |
401 // | hpp | 00 |
329 // | spp | 0 |
330 // | pie | 0000 | pie.h is used as UBE
331 // | ie | 0000 | uie hardlinked to 0, as N ext is not implemented
332
333 val mstatusStruct = mstatus.asTypeOf(new MstatusStruct)
334 def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
335 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
402 // | spp | 0 |
403 // | pie | 0000 | pie.h is used as UBE
404 // | ie | 0000 | uie hardlinked to 0, as N ext is not implemented
405
406 val mstatusStruct = mstatus.asTypeOf(new MstatusStruct)
407 def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
408 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
336 // Cat(sd, other)
337 val mstatusNew = Cat(
338 mstatusOld.xs === ContextStatus.dirty || mstatusOld.fs === ContextStatus.dirty || mstatusOld.vs === ContextStatus.dirty,
339 mstatus(XLEN-2, 0)
340 )
409 val mstatusNew = Cat(mstatusOld.xs === "b11".U || mstatusOld.fs === "b11".U, mstatus(XLEN-2, 0))
341 mstatusNew
342 }
343
344 val mstatusWMask = (~ZeroExt((
410 mstatusNew
411 }
412
413 val mstatusWMask = (~ZeroExt((
345 GenMask(63) | // SD is read-only
346 GenMask(62, 36) | // WPRI
414 GenMask(XLEN - 2, 36) | // WPRI
347 GenMask(35, 32) | // SXL and UXL cannot be changed
348 GenMask(31, 23) | // WPRI
349 GenMask(16, 15) | // XS is read-only
415 GenMask(35, 32) | // SXL and UXL cannot be changed
416 GenMask(31, 23) | // WPRI
417 GenMask(16, 15) | // XS is read-only
418 GenMask(10, 9) | // VS, not supported yet
350 GenMask(6) | // UBE, always little-endian (0)
351 GenMask(4) | // WPRI
352 GenMask(2) | // WPRI
353 GenMask(0) // WPRI
354 ), 64)).asUInt
355
356 val medeleg = RegInit(UInt(XLEN.W), 0.U)
357 val mideleg = RegInit(UInt(XLEN.W), 0.U)
358 val mscratch = RegInit(UInt(XLEN.W), 0.U)
359
360 // PMP Mapping
361 val pmp = Wire(Vec(NumPMP, new PMPEntry())) // just used for method parameter
362 val pma = Wire(Vec(NumPMA, new PMPEntry())) // just used for method parameter
363 val pmpMapping = pmp_gen_mapping(pmp_init, NumPMP, PmpcfgBase, PmpaddrBase, pmp)
364 val pmaMapping = pmp_gen_mapping(pma_init, NumPMA, PmacfgBase, PmaaddrBase, pma)
365
366 // Superviser-Level CSRs
367
419 GenMask(6) | // UBE, always little-endian (0)
420 GenMask(4) | // WPRI
421 GenMask(2) | // WPRI
422 GenMask(0) // WPRI
423 ), 64)).asUInt
424
425 val medeleg = RegInit(UInt(XLEN.W), 0.U)
426 val mideleg = RegInit(UInt(XLEN.W), 0.U)
427 val mscratch = RegInit(UInt(XLEN.W), 0.U)
428
429 // PMP Mapping
430 val pmp = Wire(Vec(NumPMP, new PMPEntry())) // just used for method parameter
431 val pma = Wire(Vec(NumPMA, new PMPEntry())) // just used for method parameter
432 val pmpMapping = pmp_gen_mapping(pmp_init, NumPMP, PmpcfgBase, PmpaddrBase, pmp)
433 val pmaMapping = pmp_gen_mapping(pma_init, NumPMA, PmacfgBase, PmaaddrBase, pma)
434
435 // Superviser-Level CSRs
436
368 val sstatusWNmask: BigInt = (
369 BigIntGenMask(63) | // SD is read-only
370 BigIntGenMask(62, 34) | // WPRI
371 BigIntGenMask(33, 32) | // UXL is hard-wired to 64(b10)
372 BigIntGenMask(31, 20) | // WPRI
373 BigIntGenMask(17) | // WPRI
374 BigIntGenMask(16, 15) | // XS is read-only to zero
375 BigIntGenMask(12, 11) | // WPRI
376 BigIntGenMask(7) | // WPRI
377 BigIntGenMask(6) | // UBE is always little-endian (0)
378 BigIntGenMask(4, 2) | // WPRI
379 BigIntGenMask(0) // WPRI
380 )
381
382 val sstatusWmask = BigIntNot(sstatusWNmask).U(XLEN.W)
383 val sstatusRmask = (
384 BigIntGenMask(63) | // SD
385 BigIntGenMask(33, 32) | // UXL
386 BigIntGenMask(19) | // MXR
387 BigIntGenMask(18) | // SUM
388 BigIntGenMask(16, 15) | // XS
389 BigIntGenMask(14, 13) | // FS
390 BigIntGenMask(10, 9 ) | // VS
391 BigIntGenMask(8) | // SPP
392 BigIntGenMask(6) | // UBE: hard wired to 0
393 BigIntGenMask(5) | // SPIE
394 BigIntGenMask(1)
395 ).U(XLEN.W)
396
397 println(s"sstatusWNmask: 0x${sstatusWNmask.toString(16)}")
398 println(s"sstatusWmask: 0x${sstatusWmask.litValue.toString(16)}")
399 println(s"sstatusRmask: 0x${sstatusRmask.litValue.toString(16)}")
400
437 // val sstatus = RegInit(UInt(XLEN.W), "h00000000".U)
438 val sstatusWmask = "hc6122".U(XLEN.W)
439 // Sstatus Write Mask
440 // -------------------------------------------------------
441 // 19 9 5 2
442 // 0 1100 0000 0001 0010 0010
443 // 0 c 0 1 2 2
444 // -------------------------------------------------------
445 val sstatusRmask = sstatusWmask | "h8000000300018000".U
446 // Sstatus Read Mask = (SSTATUS_WMASK | (0xf << 13) | (1ull << 63) | (3ull << 32))
401 // stvec: {BASE (WARL), MODE (WARL)} where mode is 0 or 1
402 val stvecMask = ~(0x2.U(XLEN.W))
403 val stvec = RegInit(UInt(XLEN.W), 0.U)
404 // val sie = RegInit(0.U(XLEN.W))
405 val sieMask = "h222".U & mideleg
406 val sipMask = "h222".U & mideleg
407 val sipWMask = "h2".U(XLEN.W) // ssip is writeable in smode
408 val satp = if(EnbaleTlbDebug) RegInit(UInt(XLEN.W), "h8000000000087fbe".U) else RegInit(0.U(XLEN.W))

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469 // sdsid: Differentiated Services ID
470 val sdsid = RegInit(UInt(XLEN.W), 0.U)
471 csrio.customCtrl.dsid := sdsid
472
473 // slvpredctl: load violation predict settings
474 // Default reset period: 2^16
475 // Why this number: reset more frequently while keeping the overhead low
476 // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead
447 // stvec: {BASE (WARL), MODE (WARL)} where mode is 0 or 1
448 val stvecMask = ~(0x2.U(XLEN.W))
449 val stvec = RegInit(UInt(XLEN.W), 0.U)
450 // val sie = RegInit(0.U(XLEN.W))
451 val sieMask = "h222".U & mideleg
452 val sipMask = "h222".U & mideleg
453 val sipWMask = "h2".U(XLEN.W) // ssip is writeable in smode
454 val satp = if(EnbaleTlbDebug) RegInit(UInt(XLEN.W), "h8000000000087fbe".U) else RegInit(0.U(XLEN.W))

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515 // sdsid: Differentiated Services ID
516 val sdsid = RegInit(UInt(XLEN.W), 0.U)
517 csrio.customCtrl.dsid := sdsid
518
519 // slvpredctl: load violation predict settings
520 // Default reset period: 2^16
521 // Why this number: reset more frequently while keeping the overhead low
522 // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead
477 val slvpredctl = Reg(UInt(XLEN.W))
478 when(reset.asBool) {
479 slvpredctl := Constantin.createRecord("slvpredctl", "h60".U)
480 }
523 val slvpredctl = RegInit(UInt(XLEN.W), "h60".U)
481 csrio.customCtrl.lvpred_disable := slvpredctl(0)
482 csrio.customCtrl.no_spec_load := slvpredctl(1)
483 csrio.customCtrl.storeset_wait_store := slvpredctl(2)
484 csrio.customCtrl.storeset_no_fast_wakeup := slvpredctl(3)
485 csrio.customCtrl.lvpred_timeout := slvpredctl(8, 4)
486
487 // smblockctl: memory block configurations
488 // +------------------------------+---+----+----+-----+--------+

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497 // Bit 6 : Enable cache error after reset (CE).
498 // Bit 7 : Enable uncache write outstanding (O).
499 // Others : Reserved.
500
501 val smblockctl_init_val =
502 (0xf & StoreBufferThreshold) |
503 (EnableLdVioCheckAfterReset.toInt << 4) |
504 (EnableSoftPrefetchAfterReset.toInt << 5) |
524 csrio.customCtrl.lvpred_disable := slvpredctl(0)
525 csrio.customCtrl.no_spec_load := slvpredctl(1)
526 csrio.customCtrl.storeset_wait_store := slvpredctl(2)
527 csrio.customCtrl.storeset_no_fast_wakeup := slvpredctl(3)
528 csrio.customCtrl.lvpred_timeout := slvpredctl(8, 4)
529
530 // smblockctl: memory block configurations
531 // +------------------------------+---+----+----+-----+--------+

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540 // Bit 6 : Enable cache error after reset (CE).
541 // Bit 7 : Enable uncache write outstanding (O).
542 // Others : Reserved.
543
544 val smblockctl_init_val =
545 (0xf & StoreBufferThreshold) |
546 (EnableLdVioCheckAfterReset.toInt << 4) |
547 (EnableSoftPrefetchAfterReset.toInt << 5) |
505 (EnableCacheErrorAfterReset.toInt << 6) |
548 (EnableCacheErrorAfterReset.toInt << 6)
506 (EnableUncacheWriteOutstanding.toInt << 7)
507 val smblockctl = RegInit(UInt(XLEN.W), smblockctl_init_val.U)
508 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
509 // bits 4: enable load load violation check
510 csrio.customCtrl.ldld_vio_check_enable := smblockctl(4)
511 csrio.customCtrl.soft_prefetch_enable := smblockctl(5)
512 csrio.customCtrl.cache_error_enable := smblockctl(6)
513 csrio.customCtrl.uncache_write_outstanding_enable := smblockctl(7)

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571 }
572
573 val fcsrMapping = Map(
574 MaskedRegMap(Fflags, fcsr, wfn = fflags_wfn(update = false), rfn = fflags_rfn),
575 MaskedRegMap(Frm, fcsr, wfn = frm_wfn, rfn = frm_rfn),
576 MaskedRegMap(Fcsr, fcsr, wfn = fcsr_wfn)
577 )
578
549 (EnableUncacheWriteOutstanding.toInt << 7)
550 val smblockctl = RegInit(UInt(XLEN.W), smblockctl_init_val.U)
551 csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
552 // bits 4: enable load load violation check
553 csrio.customCtrl.ldld_vio_check_enable := smblockctl(4)
554 csrio.customCtrl.soft_prefetch_enable := smblockctl(5)
555 csrio.customCtrl.cache_error_enable := smblockctl(6)
556 csrio.customCtrl.uncache_write_outstanding_enable := smblockctl(7)

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614 }
615
616 val fcsrMapping = Map(
617 MaskedRegMap(Fflags, fcsr, wfn = fflags_wfn(update = false), rfn = fflags_rfn),
618 MaskedRegMap(Frm, fcsr, wfn = frm_wfn, rfn = frm_rfn),
619 MaskedRegMap(Fcsr, fcsr, wfn = fcsr_wfn)
620 )
621
579 // Vector extension CSRs
580 val vstart = RegInit(0.U(XLEN.W))
581 val vcsr = RegInit(0.U(XLEN.W))
582 val vl = Reg(UInt(XLEN.W))
583 val vtype = Reg(UInt(XLEN.W))
584 val vlenb = RegInit((VLEN / 8).U(XLEN.W))
585
586 // set mstatus->sd and mstatus->vs when true
587 val csrw_dirty_vs_state = WireInit(false.B)
588
589 // vcsr is mapped to vxrm and vxsat
590 class VcsrStruct extends Bundle {
591 val reserved = UInt((XLEN-3).W)
592 val vxrm = UInt(2.W)
593 val vxsat = UInt(1.W)
594 assert(this.getWidth == XLEN)
595 }
596
597 def vxrm_wfn(wdata: UInt): UInt = {
598 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
599 csrw_dirty_vs_state := true.B
600 vcsrOld.vxrm := wdata(1,0)
601 vcsrOld.asUInt
602 }
603 def vxrm_rfn(rdata: UInt): UInt = rdata(2,1)
604
605 def vxsat_wfn(update: Boolean)(wdata: UInt): UInt = {
606 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
607 val vcsrNew = WireInit(vcsrOld)
608 csrw_dirty_vs_state := true.B
609 if (update) {
610 vcsrNew.vxsat := wdata(0) | vcsrOld.vxsat
611 } else {
612 vcsrNew.vxsat := wdata(0)
613 }
614 vcsrNew.asUInt
615 }
616 def vxsat_rfn(rdata: UInt): UInt = rdata(0)
617
618 def vcsr_wfn(wdata: UInt): UInt = {
619 val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
620 csrw_dirty_vs_state := true.B
621 vcsrOld.vxrm := wdata.asTypeOf(vcsrOld).vxrm
622 vcsrOld.vxsat := wdata.asTypeOf(vcsrOld).vxsat
623 vcsrOld.asUInt
624 }
625
626 val vcsrMapping = Map(
627 MaskedRegMap(Vstart, vstart),
628 MaskedRegMap(Vxrm, vcsr, wfn = vxrm_wfn, rfn = vxrm_rfn),
629 MaskedRegMap(Vxsat, vcsr, wfn = vxsat_wfn(false), rfn = vxsat_rfn),
630 MaskedRegMap(Vcsr, vcsr, wfn = vcsr_wfn),
631 MaskedRegMap(Vl, vl),
632 MaskedRegMap(Vtype, vtype),
633 MaskedRegMap(Vlenb, vlenb),
634 )
635
636 // Hart Priviledge Mode
637 val priviledgeMode = RegInit(UInt(2.W), ModeM)
638
639 //val perfEventscounten = List.fill(nrPerfCnts)(RegInit(false(Bool())))
640 // Perf Counter
641 val nrPerfCnts = 29 // 3...31
642 val priviledgeModeOH = UIntToOH(priviledgeMode)
643 val perfEventscounten = RegInit(0.U.asTypeOf(Vec(nrPerfCnts, Bool())))

--- 32 unchanged lines hidden (view full) ---

676 minstret := minstret + RegNext(csrio.perf.retiredInstr)
677 for(i <- 0 until 29){
678 perfCnts(i) := Mux(mcountinhibit(i+3) | !perfEventscounten(i), perfCnts(i), perfCnts(i) + perf_events(i).value)
679 }
680
681 // CSR reg map
682 val basicPrivMapping = Map(
683
622 // Hart Priviledge Mode
623 val priviledgeMode = RegInit(UInt(2.W), ModeM)
624
625 //val perfEventscounten = List.fill(nrPerfCnts)(RegInit(false(Bool())))
626 // Perf Counter
627 val nrPerfCnts = 29 // 3...31
628 val priviledgeModeOH = UIntToOH(priviledgeMode)
629 val perfEventscounten = RegInit(0.U.asTypeOf(Vec(nrPerfCnts, Bool())))

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662 minstret := minstret + RegNext(csrio.perf.retiredInstr)
663 for(i <- 0 until 29){
664 perfCnts(i) := Mux(mcountinhibit(i+3) | !perfEventscounten(i), perfCnts(i), perfCnts(i) + perf_events(i).value)
665 }
666
667 // CSR reg map
668 val basicPrivMapping = Map(
669
684 // Unprivileged Floating-Point CSRs
685 // Has been mapped above
670 //--- User Trap Setup ---
671 // MaskedRegMap(Ustatus, ustatus),
672 // MaskedRegMap(Uie, uie, 0.U, MaskedRegMap.Unwritable),
673 // MaskedRegMap(Utvec, utvec),
686
674
687 // Unprivileged Counter/Timers
688 MaskedRegMap(Cycle, mcycle),
689 // We don't support read time CSR.
690 // MaskedRegMap(Time, mtime),
691 MaskedRegMap(Instret, minstret),
675 //--- User Trap Handling ---
676 // MaskedRegMap(Uscratch, uscratch),
677 // MaskedRegMap(Uepc, uepc),
678 // MaskedRegMap(Ucause, ucause),
679 // MaskedRegMap(Utval, utval),
680 // MaskedRegMap(Uip, uip),
692
681
682 //--- User Counter/Timers ---
683 // MaskedRegMap(Cycle, cycle),
684 // MaskedRegMap(Time, time),
685 // MaskedRegMap(Instret, instret),
686
693 //--- Supervisor Trap Setup ---
694 MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
695 // MaskedRegMap(Sedeleg, Sedeleg),
696 // MaskedRegMap(Sideleg, Sideleg),
697 MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
698 MaskedRegMap(Stvec, stvec, stvecMask, MaskedRegMap.NoSideEffect, stvecMask),
699 MaskedRegMap(Scounteren, scounteren),
700

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737 MaskedRegMap(Mscratch, mscratch),
738 MaskedRegMap(Mepc, mepc, mepcMask, MaskedRegMap.NoSideEffect, mepcMask),
739 MaskedRegMap(Mcause, mcause),
740 MaskedRegMap(Mtval, mtval),
741 MaskedRegMap(Mip, mip.asUInt, 0.U(XLEN.W), MaskedRegMap.Unwritable),
742
743 //--- Trigger ---
744 MaskedRegMap(Tselect, tselectPhy, WritableMask, WriteTselect),
687 //--- Supervisor Trap Setup ---
688 MaskedRegMap(Sstatus, mstatus, sstatusWmask, mstatusUpdateSideEffect, sstatusRmask),
689 // MaskedRegMap(Sedeleg, Sedeleg),
690 // MaskedRegMap(Sideleg, Sideleg),
691 MaskedRegMap(Sie, mie, sieMask, MaskedRegMap.NoSideEffect, sieMask),
692 MaskedRegMap(Stvec, stvec, stvecMask, MaskedRegMap.NoSideEffect, stvecMask),
693 MaskedRegMap(Scounteren, scounteren),
694

--- 36 unchanged lines hidden (view full) ---

731 MaskedRegMap(Mscratch, mscratch),
732 MaskedRegMap(Mepc, mepc, mepcMask, MaskedRegMap.NoSideEffect, mepcMask),
733 MaskedRegMap(Mcause, mcause),
734 MaskedRegMap(Mtval, mtval),
735 MaskedRegMap(Mip, mip.asUInt, 0.U(XLEN.W), MaskedRegMap.Unwritable),
736
737 //--- Trigger ---
738 MaskedRegMap(Tselect, tselectPhy, WritableMask, WriteTselect),
745 // Todo: support chain length = 2
746 MaskedRegMap(Tdata1, tdata1RegVec(tselectPhy),
747 WritableMask,
748 x => Tdata1Bundle.Write(x, tdata1RegVec(tselectPhy), newTriggerChainIsLegal, debug_mode = debugMode),
749 WritableMask,
750 x => Tdata1Bundle.Read(x)),
751 MaskedRegMap(Tdata2, tdata2RegVec(tselectPhy)),
739 MaskedRegMap(Tdata1, tdata1Phy(tselectPhy), WritableMask, WriteTdata1, WritableMask, ReadTdata1),
740 MaskedRegMap(Tdata2, tdata2Phy(tselectPhy)),
752 MaskedRegMap(Tinfo, tinfo, 0.U(XLEN.W), MaskedRegMap.Unwritable),
741 MaskedRegMap(Tinfo, tinfo, 0.U(XLEN.W), MaskedRegMap.Unwritable),
742 MaskedRegMap(Tcontrol, tControlPhy, tcontrolWriteMask),
753
754 //--- Debug Mode ---
755 MaskedRegMap(Dcsr, dcsr, dcsrMask, dcsrUpdateSideEffect),
756 MaskedRegMap(Dpc, dpc),
743
744 //--- Debug Mode ---
745 MaskedRegMap(Dcsr, dcsr, dcsrMask, dcsrUpdateSideEffect),
746 MaskedRegMap(Dpc, dpc),
757 MaskedRegMap(Dscratch0, dscratch0),
747 MaskedRegMap(Dscratch, dscratch),
758 MaskedRegMap(Dscratch1, dscratch1),
759 MaskedRegMap(Mcountinhibit, mcountinhibit),
760 MaskedRegMap(Mcycle, mcycle),
761 MaskedRegMap(Minstret, minstret),
762 )
763
764 val perfCntMapping = (0 until 29).map(i => {Map(
765 MaskedRegMap(addr = Mhpmevent3 +i,
766 reg = perfEvents(i),
767 wmask = "hf87fff3fcff3fcff".U(XLEN.W)),
768 MaskedRegMap(addr = Mhpmcounter3 +i,
748 MaskedRegMap(Dscratch1, dscratch1),
749 MaskedRegMap(Mcountinhibit, mcountinhibit),
750 MaskedRegMap(Mcycle, mcycle),
751 MaskedRegMap(Minstret, minstret),
752 )
753
754 val perfCntMapping = (0 until 29).map(i => {Map(
755 MaskedRegMap(addr = Mhpmevent3 +i,
756 reg = perfEvents(i),
757 wmask = "hf87fff3fcff3fcff".U(XLEN.W)),
758 MaskedRegMap(addr = Mhpmcounter3 +i,
769 reg = perfCnts(i)),
770 MaskedRegMap(addr = Hpmcounter3 + i,
771 reg = perfCnts(i))
772 )}).fold(Map())((a,b) => a ++ b)
773 // TODO: mechanism should be implemented later
774 // val MhpmcounterStart = Mhpmcounter3
775 // val MhpmeventStart = Mhpmevent3
776 // for (i <- 0 until nrPerfCnts) {
777 // perfCntMapping += MaskedRegMap(MhpmcounterStart + i, perfCnts(i))
778 // perfCntMapping += MaskedRegMap(MhpmeventStart + i, perfEvents(i))

--- 9 unchanged lines hidden (view full) ---

788 )
789 }}
790
791 val mapping = basicPrivMapping ++
792 perfCntMapping ++
793 pmpMapping ++
794 pmaMapping ++
795 (if (HasFPU) fcsrMapping else Nil) ++
759 reg = perfCnts(i))
760 )}).fold(Map())((a,b) => a ++ b)
761 // TODO: mechanism should be implemented later
762 // val MhpmcounterStart = Mhpmcounter3
763 // val MhpmeventStart = Mhpmevent3
764 // for (i <- 0 until nrPerfCnts) {
765 // perfCntMapping += MaskedRegMap(MhpmcounterStart + i, perfCnts(i))
766 // perfCntMapping += MaskedRegMap(MhpmeventStart + i, perfEvents(i))

--- 9 unchanged lines hidden (view full) ---

776 )
777 }}
778
779 val mapping = basicPrivMapping ++
780 perfCntMapping ++
781 pmpMapping ++
782 pmaMapping ++
783 (if (HasFPU) fcsrMapping else Nil) ++
796 (if (HasVPU) vcsrMapping else Nil) ++
797 (if (HasCustomCSRCacheOp) cacheopMapping else Nil)
798
784 (if (HasCustomCSRCacheOp) cacheopMapping else Nil)
785
799
800 println("XiangShan CSR Lists")
801
802 for (addr <- mapping.keys.toSeq.sorted) {
803 println(f"$addr%#03x ${mapping(addr)._1}")
804 }
805
806 val addr = src2(11, 0)
807 val csri = ZeroExt(src2(16, 12), XLEN)
808 val rdata = Wire(UInt(XLEN.W))
809 val wdata = LookupTree(func, List(
810 CSROpType.wrt -> src1,
811 CSROpType.set -> (rdata | src1),
812 CSROpType.clr -> (rdata & (~src1).asUInt),
813 CSROpType.wrti -> csri,
814 CSROpType.seti -> (rdata | csri),
815 CSROpType.clri -> (rdata & (~csri).asUInt)
816 ))
817
818 val addrInPerfCnt = (addr >= Mcycle.U) && (addr <= Mhpmcounter31.U) ||
819 (addr >= Mcountinhibit.U) && (addr <= Mhpmevent31.U) ||
786 val addr = src2(11, 0)
787 val csri = ZeroExt(src2(16, 12), XLEN)
788 val rdata = Wire(UInt(XLEN.W))
789 val wdata = LookupTree(func, List(
790 CSROpType.wrt -> src1,
791 CSROpType.set -> (rdata | src1),
792 CSROpType.clr -> (rdata & (~src1).asUInt),
793 CSROpType.wrti -> csri,
794 CSROpType.seti -> (rdata | csri),
795 CSROpType.clri -> (rdata & (~csri).asUInt)
796 ))
797
798 val addrInPerfCnt = (addr >= Mcycle.U) && (addr <= Mhpmcounter31.U) ||
799 (addr >= Mcountinhibit.U) && (addr <= Mhpmevent31.U) ||
820 (addr >= Cycle.U) && (addr <= Hpmcounter31.U) ||
821 addr === Mip.U
822 csrio.isPerfCnt := addrInPerfCnt && valid && func =/= CSROpType.jmp
823
824 // satp wen check
825 val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
826
827 // csr access check, special case
828 val tvmNotPermit = (priviledgeMode === ModeS && mstatusStruct.tvm.asBool)

--- 4 unchanged lines hidden (view full) ---

833 val wen = valid && CSROpType.needAccess(func) && (addr=/=Satp.U || satpLegalMode)
834 val dcsrPermitted = dcsrPermissionCheck(addr, false.B, debugMode)
835 val triggerPermitted = triggerPermissionCheck(addr, true.B, debugMode) // todo dmode
836 val modePermitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode) && dcsrPermitted && triggerPermitted
837 val perfcntPermitted = perfcntPermissionCheck(addr, priviledgeMode, mcounteren, scounteren)
838 val permitted = Mux(addrInPerfCnt, perfcntPermitted, modePermitted) && accessPermitted
839
840 MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
800 addr === Mip.U
801 csrio.isPerfCnt := addrInPerfCnt && valid && func =/= CSROpType.jmp
802
803 // satp wen check
804 val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
805
806 // csr access check, special case
807 val tvmNotPermit = (priviledgeMode === ModeS && mstatusStruct.tvm.asBool)

--- 4 unchanged lines hidden (view full) ---

812 val wen = valid && CSROpType.needAccess(func) && (addr=/=Satp.U || satpLegalMode)
813 val dcsrPermitted = dcsrPermissionCheck(addr, false.B, debugMode)
814 val triggerPermitted = triggerPermissionCheck(addr, true.B, debugMode) // todo dmode
815 val modePermitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode) && dcsrPermitted && triggerPermitted
816 val perfcntPermitted = perfcntPermissionCheck(addr, priviledgeMode, mcounteren, scounteren)
817 val permitted = Mux(addrInPerfCnt, perfcntPermitted, modePermitted) && accessPermitted
818
819 MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
841 io.out.bits.res.data := rdata
842 io.out.bits.ctrl.flushPipe.get := flushPipe
843 connectNonPipedCtrlSingal
820 io.out.bits.data := rdata
821 io.out.bits.uop := io.in.bits.uop
822 io.out.bits.uop.cf := cfOut
823 io.out.bits.uop.ctrl.flushPipe := flushPipe
844
845 // send distribute csr a w signal
846 csrio.customCtrl.distribute_csr.w.valid := wen && permitted
847 csrio.customCtrl.distribute_csr.w.bits.data := wdata
848 csrio.customCtrl.distribute_csr.w.bits.addr := addr
849
850 // Fix Mip/Sip write
851 val fixMapping = Map(

--- 9 unchanged lines hidden (view full) ---

861 CSROpType.seti -> (rdataFix | csri),
862 CSROpType.clri -> (rdataFix & (~csri).asUInt)
863 ))
864 MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
865
866 when (RegNext(csrio.fpu.fflags.valid)) {
867 fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
868 }
824
825 // send distribute csr a w signal
826 csrio.customCtrl.distribute_csr.w.valid := wen && permitted
827 csrio.customCtrl.distribute_csr.w.bits.data := wdata
828 csrio.customCtrl.distribute_csr.w.bits.addr := addr
829
830 // Fix Mip/Sip write
831 val fixMapping = Map(

--- 9 unchanged lines hidden (view full) ---

841 CSROpType.seti -> (rdataFix | csri),
842 CSROpType.clri -> (rdataFix & (~csri).asUInt)
843 ))
844 MaskedRegMap.generate(fixMapping, addr, rdataFix, wen && permitted, wdataFix)
845
846 when (RegNext(csrio.fpu.fflags.valid)) {
847 fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
848 }
869 when(RegNext(csrio.vpu.set_vxsat.valid)) {
870 vcsr := vxsat_wfn(update = true)(RegNext(csrio.vpu.set_vxsat.bits))
871 }
872 // set fs and sd in mstatus
873 when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
874 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
875 mstatusNew.fs := "b11".U
876 mstatusNew.sd := true.B
877 mstatus := mstatusNew.asUInt
878 }
879 csrio.fpu.frm := fcsr.asTypeOf(new FcsrStruct).frm
880
849 // set fs and sd in mstatus
850 when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
851 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
852 mstatusNew.fs := "b11".U
853 mstatusNew.sd := true.B
854 mstatus := mstatusNew.asUInt
855 }
856 csrio.fpu.frm := fcsr.asTypeOf(new FcsrStruct).frm
857
881 when (RegNext(csrio.vpu.set_vstart.valid)) {
882 vstart := RegNext(csrio.vpu.set_vstart.bits)
883 }
884 when (RegNext(csrio.vpu.set_vtype.valid)) {
885 vtype := RegNext(csrio.vpu.set_vtype.bits)
886 }
887 when (RegNext(csrio.vpu.set_vl.valid)) {
888 vl := RegNext(csrio.vpu.set_vl.bits)
889 }
890 // set vs and sd in mstatus
891 when(csrw_dirty_vs_state || RegNext(csrio.vpu.dirty_vs)) {
892 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
893 mstatusNew.vs := ContextStatus.dirty
894 mstatusNew.sd := true.B
895 mstatus := mstatusNew.asUInt
896 }
897
858
898 csrio.vpu.vstart := vstart
899 csrio.vpu.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
900 csrio.vpu.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
901 csrio.vpu.vcsr := vcsr
902 csrio.vpu.vtype := vtype
903 csrio.vpu.vl := vl
904 csrio.vpu.vlenb := vlenb
905 csrio.vpu.vill := vtype.asTypeOf(new VtypeStruct).vill
906 csrio.vpu.vma := vtype.asTypeOf(new VtypeStruct).vma
907 csrio.vpu.vta := vtype.asTypeOf(new VtypeStruct).vta
908 csrio.vpu.vsew := vtype.asTypeOf(new VtypeStruct).vsew
909 csrio.vpu.vlmul := vtype.asTypeOf(new VtypeStruct).vlmul
910
911 // Trigger Ctrl
859 // Trigger Ctrl
912 val triggerEnableVec = tdata1RegVec.map { tdata1 =>
913 val mcontrolData = tdata1.asTypeOf(new Tdata1Bundle).data.asTypeOf(new MControlData)
914 tdata1.asTypeOf(new Tdata1Bundle).type_.asUInt === TrigTypeEnum.MCONTROL && (
915 mcontrolData.m && priviledgeMode === ModeM ||
916 mcontrolData.s && priviledgeMode === ModeS ||
917 mcontrolData.u && priviledgeMode === ModeU)
860 csrio.customCtrl.trigger_enable := tdata1Phy.map{t =>
861 def tdata1 = t.asTypeOf(new TdataBundle)
862 tdata1.m && priviledgeMode === ModeM ||
863 tdata1.s && priviledgeMode === ModeS || tdata1.u && priviledgeMode === ModeU
918 }
864 }
919 val fetchTriggerEnableVec = triggerEnableVec.zip(tdata1WireVec).map {
920 case (tEnable, tdata1) => tEnable && tdata1.asTypeOf(new Tdata1Bundle).data.asTypeOf(new MControlData).isFetchTrigger
921 }
922 val memAccTriggerEnableVec = triggerEnableVec.zip(tdata1WireVec).map {
923 case (tEnable, tdata1) => tEnable && tdata1.asTypeOf(new Tdata1Bundle).data.asTypeOf(new MControlData).isMemAccTrigger
924 }
925 csrio.customCtrl.frontend_trigger.tEnableVec := fetchTriggerEnableVec
926 csrio.customCtrl.mem_trigger.tEnableVec := memAccTriggerEnableVec
865 csrio.customCtrl.frontend_trigger.t.valid := RegNext(wen && (addr === Tdata1.U || addr === Tdata2.U) && TypeLookup(tselectPhy) === I_Trigger)
866 csrio.customCtrl.mem_trigger.t.valid := RegNext(wen && (addr === Tdata1.U || addr === Tdata2.U) && TypeLookup(tselectPhy) =/= I_Trigger)
867 XSDebug(csrio.customCtrl.trigger_enable.asUInt.orR, p"Debug Mode: At least 1 trigger is enabled," +
868 p"trigger enable is ${Binary(csrio.customCtrl.trigger_enable.asUInt)}\n")
927
869
928 val tdata1Update = wen && (addr === Tdata1.U)
929 val tdata2Update = wen && (addr === Tdata2.U)
930 val triggerUpdate = wen && (addr === Tdata1.U || addr === Tdata2.U)
931 val frontendTriggerUpdate =
932 tdata1Update && wdata.asTypeOf(new Tdata1Bundle).type_.asUInt === TrigTypeEnum.MCONTROL &&
933 wdata.asTypeOf(new Tdata1Bundle).data.asTypeOf(new MControlData).isFetchTrigger ||
934 tdata1Selected.data.asTypeOf(new MControlData).isFetchTrigger && triggerUpdate
935 val memTriggerUpdate =
936 tdata1Update && wdata.asTypeOf(new Tdata1Bundle).type_.asUInt === TrigTypeEnum.MCONTROL &&
937 wdata.asTypeOf(new Tdata1Bundle).data.asTypeOf(new MControlData).isMemAccTrigger ||
938 tdata1Selected.data.asTypeOf(new MControlData).isMemAccTrigger && triggerUpdate
939
940 csrio.customCtrl.frontend_trigger.tUpdate.valid := RegNext(RegNext(frontendTriggerUpdate))
941 csrio.customCtrl.mem_trigger.tUpdate.valid := RegNext(RegNext(memTriggerUpdate))
942 XSDebug(triggerEnableVec.reduce(_ || _), p"Debug Mode: At least 1 trigger is enabled," +
943 p"trigger enable is ${Binary(triggerEnableVec.asUInt)}\n")
944
945 // CSR inst decode
946 val isEbreak = addr === privEbreak && func === CSROpType.jmp
947 val isEcall = addr === privEcall && func === CSROpType.jmp
948 val isMret = addr === privMret && func === CSROpType.jmp
949 val isSret = addr === privSret && func === CSROpType.jmp
950 val isUret = addr === privUret && func === CSROpType.jmp
951 val isDret = addr === privDret && func === CSROpType.jmp
952 val isWFI = func === CSROpType.wfi
953
870 // CSR inst decode
871 val isEbreak = addr === privEbreak && func === CSROpType.jmp
872 val isEcall = addr === privEcall && func === CSROpType.jmp
873 val isMret = addr === privMret && func === CSROpType.jmp
874 val isSret = addr === privSret && func === CSROpType.jmp
875 val isUret = addr === privUret && func === CSROpType.jmp
876 val isDret = addr === privDret && func === CSROpType.jmp
877 val isWFI = func === CSROpType.wfi
878
954 XSDebug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", io.in.bits.data.pc.get, addr, rdata, wdata, func)
955 XSDebug(wen, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.in.bits.data.pc.get, mstatus, mideleg , medeleg, priviledgeMode)
879 XSDebug(wen, "csr write: pc %x addr %x rdata %x wdata %x func %x\n", cfIn.pc, addr, rdata, wdata, func)
880 XSDebug(wen, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", cfIn.pc, mstatus, mideleg , medeleg, priviledgeMode)
956
957 // Illegal priviledged operation list
958 val illegalMret = valid && isMret && priviledgeMode < ModeM
959 val illegalSret = valid && isSret && priviledgeMode < ModeS
960 val illegalSModeSret = valid && isSret && priviledgeMode === ModeS && mstatusStruct.tsr.asBool
961 // When TW=1, then if WFI is executed in any less-privileged mode,
962 // and it does not complete within an implementation-specific, bounded time limit,
963 // the WFI instruction causes an illegal instruction exception.

--- 8 unchanged lines hidden (view full) ---

972
973 // expose several csr bits for tlb
974 tlbBundle.priv.mxr := mstatusStruct.mxr.asBool
975 tlbBundle.priv.sum := mstatusStruct.sum.asBool
976 tlbBundle.priv.imode := priviledgeMode
977 tlbBundle.priv.dmode := Mux(debugMode && dcsr.asTypeOf(new DcsrStruct).mprven, ModeM, Mux(mstatusStruct.mprv.asBool, mstatusStruct.mpp, priviledgeMode))
978
979 // Branch control
881
882 // Illegal priviledged operation list
883 val illegalMret = valid && isMret && priviledgeMode < ModeM
884 val illegalSret = valid && isSret && priviledgeMode < ModeS
885 val illegalSModeSret = valid && isSret && priviledgeMode === ModeS && mstatusStruct.tsr.asBool
886 // When TW=1, then if WFI is executed in any less-privileged mode,
887 // and it does not complete within an implementation-specific, bounded time limit,
888 // the WFI instruction causes an illegal instruction exception.

--- 8 unchanged lines hidden (view full) ---

897
898 // expose several csr bits for tlb
899 tlbBundle.priv.mxr := mstatusStruct.mxr.asBool
900 tlbBundle.priv.sum := mstatusStruct.sum.asBool
901 tlbBundle.priv.imode := priviledgeMode
902 tlbBundle.priv.dmode := Mux(debugMode && dcsr.asTypeOf(new DcsrStruct).mprven, ModeM, Mux(mstatusStruct.mprv.asBool, mstatusStruct.mpp, priviledgeMode))
903
904 // Branch control
980 val retTarget = WireInit(0.U)
905 val retTarget = Wire(UInt(VAddrBits.W))
981 val resetSatp = addr === Satp.U && wen // write to satp will cause the pipeline be flushed
906 val resetSatp = addr === Satp.U && wen // write to satp will cause the pipeline be flushed
907 flushPipe := resetSatp || (valid && func === CSROpType.jmp && !isEcall && !isEbreak)
982
908
983 val w_fcsr_change_rm = wen && addr === Fcsr.U && wdata(7, 5) =/= fcsr(7, 5)
984 val w_frm_change_rm = wen && addr === Frm.U && wdata(2, 0) =/= fcsr(7, 5)
985 val frm_change = w_fcsr_change_rm || w_frm_change_rm
986 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak
987 flushPipe := resetSatp || frm_change || isXRet || frontendTriggerUpdate
909 retTarget := DontCare
910 // val illegalEret = TODO
988
911
912 when (valid && isDret) {
913 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
914 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
915 val dcsrNew = WireInit(dcsr.asTypeOf(new DcsrStruct))
916 val debugModeNew = WireInit(debugMode)
917 when (dcsr.asTypeOf(new DcsrStruct).prv =/= ModeM) {mstatusNew.mprv := 0.U} //If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.
918 mstatus := mstatusNew.asUInt
919 priviledgeMode := dcsrNew.prv
920 retTarget := dpc(VAddrBits-1, 0)
921 debugModeNew := false.B
922 debugIntrEnable := true.B
923 debugMode := debugModeNew
924 XSDebug("Debug Mode: Dret executed, returning to %x.", retTarget)
925 }
989
926
990 private val illegalRetTarget = WireInit(false.B)
927 when (valid && isMret && !illegalMret) {
928 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
929 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
930 mstatusNew.ie.m := mstatusOld.pie.m
931 priviledgeMode := mstatusOld.mpp
932 mstatusNew.pie.m := true.B
933 mstatusNew.mpp := ModeU
934 when (mstatusOld.mpp =/= ModeM) { mstatusNew.mprv := 0.U }
935 mstatus := mstatusNew.asUInt
936 // lr := false.B
937 retTarget := mepc(VAddrBits-1, 0)
938 }
991
939
992 // Mux tree for wires
993 when(valid) {
994 when(isDret) {
995 retTarget := dpc(VAddrBits - 1, 0)
996 }.elsewhen(isMret && !illegalMret) {
997 retTarget := mepc(VAddrBits - 1, 0)
998 }.elsewhen(isSret && !illegalSret && !illegalSModeSret) {
999 retTarget := sepc(VAddrBits - 1, 0)
1000 }.elsewhen(isUret) {
1001 retTarget := uepc(VAddrBits - 1, 0)
1002 }.otherwise {
1003 illegalRetTarget := true.B
1004 }
1005 }.otherwise {
1006 illegalRetTarget := true.B // when illegalRetTarget setted, retTarget should never be used
940 when (valid && isSret && !illegalSret && !illegalSModeSret) {
941 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
942 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
943 mstatusNew.ie.s := mstatusOld.pie.s
944 priviledgeMode := Cat(0.U(1.W), mstatusOld.spp)
945 mstatusNew.pie.s := true.B
946 mstatusNew.spp := ModeU
947 mstatus := mstatusNew.asUInt
948 when (mstatusOld.spp =/= ModeM) { mstatusNew.mprv := 0.U }
949 // lr := false.B
950 retTarget := sepc(VAddrBits-1, 0)
1007 }
1008
951 }
952
1009 // Mux tree for regs
1010 when(valid) {
1011 when(isDret) {
1012 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1013 val debugModeNew = WireInit(debugMode)
1014 when(dcsr.asTypeOf(new DcsrStruct).prv =/= ModeM) {
1015 mstatusNew.mprv := 0.U
1016 } //If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.
1017 mstatus := mstatusNew.asUInt
1018 priviledgeMode := dcsr.asTypeOf(new DcsrStruct).prv
1019 debugModeNew := false.B
1020 debugIntrEnable := true.B
1021 debugMode := debugModeNew
1022 XSDebug("Debug Mode: Dret executed, returning to %x.", retTarget)
1023 }.elsewhen(isMret && !illegalMret) {
1024 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
1025 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1026 mstatusNew.ie.m := mstatusOld.pie.m
1027 priviledgeMode := mstatusOld.mpp
1028 mstatusNew.pie.m := true.B
1029 mstatusNew.mpp := ModeU
1030 when(mstatusOld.mpp =/= ModeM) {
1031 mstatusNew.mprv := 0.U
1032 }
1033 mstatus := mstatusNew.asUInt
1034 }.elsewhen(isSret && !illegalSret && !illegalSModeSret) {
1035 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
1036 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1037 mstatusNew.ie.s := mstatusOld.pie.s
1038 priviledgeMode := Cat(0.U(1.W), mstatusOld.spp)
1039 mstatusNew.pie.s := true.B
1040 mstatusNew.spp := ModeU
1041 mstatus := mstatusNew.asUInt
1042 when(mstatusOld.spp =/= ModeM) {
1043 mstatusNew.mprv := 0.U
1044 }
1045 }.elsewhen(isUret) {
1046 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
1047 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1048 // mstatusNew.mpp.m := ModeU //TODO: add mode U
1049 mstatusNew.ie.u := mstatusOld.pie.u
1050 priviledgeMode := ModeU
1051 mstatusNew.pie.u := true.B
1052 mstatus := mstatusNew.asUInt
1053 }
953 when (valid && isUret) {
954 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
955 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
956 // mstatusNew.mpp.m := ModeU //TODO: add mode U
957 mstatusNew.ie.u := mstatusOld.pie.u
958 priviledgeMode := ModeU
959 mstatusNew.pie.u := true.B
960 mstatus := mstatusNew.asUInt
961 retTarget := uepc(VAddrBits-1, 0)
1054 }
1055
1056 io.in.ready := true.B
1057 io.out.valid := valid
1058
962 }
963
964 io.in.ready := true.B
965 io.out.valid := valid
966
1059 // In this situation, hart will enter debug mode instead of handling a breakpoint exception simply.
1060 // Ebreak block instructions backwards, so it's ok to not keep extra info to distinguish between breakpoint
1061 // exception and enter-debug-mode exception.
1062 val ebreakEnterDebugMode =
1063 (priviledgeMode === ModeM && dcsrData.ebreakm) ||
1064 (priviledgeMode === ModeS && dcsrData.ebreaks) ||
1065 (priviledgeMode === ModeU && dcsrData.ebreaku)
967 val ebreakCauseException = (priviledgeMode === ModeM && dcsrData.ebreakm) || (priviledgeMode === ModeS && dcsrData.ebreaks) || (priviledgeMode === ModeU && dcsrData.ebreaku)
1066
968
1067 // raise a debug exception waiting to enter debug mode, instead of a breakpoint exception
1068 val raiseDebugException = !debugMode && isEbreak && ebreakEnterDebugMode
1069
1070 val csrExceptionVec = WireInit(0.U.asTypeOf(ExceptionVec()))
1071 csrExceptionVec(breakPoint) := io.in.valid && isEbreak
969 val csrExceptionVec = WireInit(cfIn.exceptionVec)
970 csrExceptionVec(breakPoint) := io.in.valid && isEbreak && (ebreakCauseException || debugMode)
1072 csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
1073 csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
1074 csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
1075 // Trigger an illegal instr exception when:
1076 // * unimplemented csr is being read/written
1077 // * csr access is illegal
1078 csrExceptionVec(illegalInstr) := isIllegalAddr || isIllegalAccess || isIllegalPrivOp
971 csrExceptionVec(ecallM) := priviledgeMode === ModeM && io.in.valid && isEcall
972 csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall
973 csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall
974 // Trigger an illegal instr exception when:
975 // * unimplemented csr is being read/written
976 // * csr access is illegal
977 csrExceptionVec(illegalInstr) := isIllegalAddr || isIllegalAccess || isIllegalPrivOp
1079 io.out.bits.ctrl.exceptionVec.get := csrExceptionVec
978 cfOut.exceptionVec := csrExceptionVec
1080
979
1081 XSDebug(io.in.valid, s"Debug Mode: an Ebreak is executed, ebreak cause enter-debug-mode exception ? ${raiseDebugException}\n")
980 XSDebug(io.in.valid && isEbreak, s"Debug Mode: an Ebreak is executed, ebreak cause exception ? ${ebreakCauseException}\n")
1082
1083 /**
1084 * Exception and Intr
1085 */
1086 val ideleg = (mideleg & mip.asUInt)
1087 def priviledgedEnableDetect(x: Bool): Bool = Mux(x, ((priviledgeMode === ModeS) && mstatusStruct.ie.s) || (priviledgeMode < ModeS),
1088 ((priviledgeMode === ModeM) && mstatusStruct.ie.m) || (priviledgeMode < ModeM))
1089

--- 13 unchanged lines hidden (view full) ---

1103 csrio.wfi_event := debugIntr || (mie(11, 0) & mip.asUInt).orR
1104 mipWire.t.m := csrio.externalInterrupt.mtip
1105 mipWire.s.m := csrio.externalInterrupt.msip
1106 mipWire.e.m := csrio.externalInterrupt.meip
1107 mipWire.e.s := csrio.externalInterrupt.seip
1108
1109 // interrupts
1110 val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))
981
982 /**
983 * Exception and Intr
984 */
985 val ideleg = (mideleg & mip.asUInt)
986 def priviledgedEnableDetect(x: Bool): Bool = Mux(x, ((priviledgeMode === ModeS) && mstatusStruct.ie.s) || (priviledgeMode < ModeS),
987 ((priviledgeMode === ModeM) && mstatusStruct.ie.m) || (priviledgeMode < ModeM))
988

--- 13 unchanged lines hidden (view full) ---

1002 csrio.wfi_event := debugIntr || (mie(11, 0) & mip.asUInt).orR
1003 mipWire.t.m := csrio.externalInterrupt.mtip
1004 mipWire.s.m := csrio.externalInterrupt.msip
1005 mipWire.e.m := csrio.externalInterrupt.meip
1006 mipWire.e.s := csrio.externalInterrupt.seip
1007
1008 // interrupts
1009 val intrNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(intrVec(i), i.U, sum))
1111 val hasIntr = csrio.exception.valid && csrio.exception.bits.isInterrupt
1010 val raiseIntr = csrio.exception.valid && csrio.exception.bits.isInterrupt
1112 val ivmEnable = tlbBundle.priv.imode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1011 val ivmEnable = tlbBundle.priv.imode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1113 val iexceptionPC = Mux(ivmEnable, SignExt(csrio.exception.bits.pc, XLEN), csrio.exception.bits.pc)
1012 val iexceptionPC = Mux(ivmEnable, SignExt(csrio.exception.bits.uop.cf.pc, XLEN), csrio.exception.bits.uop.cf.pc)
1114 val dvmEnable = tlbBundle.priv.dmode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1013 val dvmEnable = tlbBundle.priv.dmode < ModeM && satp.asTypeOf(new SatpStruct).mode === 8.U
1115 val dexceptionPC = Mux(dvmEnable, SignExt(csrio.exception.bits.pc, XLEN), csrio.exception.bits.pc)
1116 XSDebug(hasIntr, "interrupt: pc=0x%x, %d\n", dexceptionPC, intrNO)
1117 val hasDebugIntr = intrNO === IRQ_DEBUG.U && hasIntr
1014 val dexceptionPC = Mux(dvmEnable, SignExt(csrio.exception.bits.uop.cf.pc, XLEN), csrio.exception.bits.uop.cf.pc)
1015 XSDebug(raiseIntr, "interrupt: pc=0x%x, %d\n", dexceptionPC, intrNO)
1016 val raiseDebugIntr = intrNO === IRQ_DEBUG.U && raiseIntr
1118
1017
1119 // exceptions from rob need to handle
1120 val exceptionVecFromRob = csrio.exception.bits.exceptionVec
1121 val hasException = csrio.exception.valid && !csrio.exception.bits.isInterrupt
1122 val hasInstrPageFault = hasException && exceptionVecFromRob(instrPageFault)
1123 val hasLoadPageFault = hasException && exceptionVecFromRob(loadPageFault)
1124 val hasStorePageFault = hasException && exceptionVecFromRob(storePageFault)
1125 val hasStoreAddrMisalign = hasException && exceptionVecFromRob(storeAddrMisaligned)
1126 val hasLoadAddrMisalign = hasException && exceptionVecFromRob(loadAddrMisaligned)
1127 val hasInstrAccessFault = hasException && exceptionVecFromRob(instrAccessFault)
1128 val hasLoadAccessFault = hasException && exceptionVecFromRob(loadAccessFault)
1129 val hasStoreAccessFault = hasException && exceptionVecFromRob(storeAccessFault)
1130 val hasBreakPoint = hasException && exceptionVecFromRob(breakPoint)
1131 val hasSingleStep = hasException && csrio.exception.bits.singleStep
1132 val hasTriggerFire = hasException && csrio.exception.bits.trigger.canFire
1133 val triggerFrontendHitVec = csrio.exception.bits.trigger.frontendHit
1134 val triggerMemHitVec = csrio.exception.bits.trigger.backendHit
1135 val triggerHitVec = triggerFrontendHitVec | triggerMemHitVec // Todo: update mcontrol.hit
1136 val triggerCanFireVec = csrio.exception.bits.trigger.frontendCanFire | csrio.exception.bits.trigger.backendCanFire
1137 // More than one triggers can hit at the same time, but only fire one
1138 // We select the first hit trigger to fire
1139 val triggerFireOH = PriorityEncoderOH(triggerCanFireVec)
1140 val triggerFireAction = PriorityMux(triggerFireOH, tdata1WireVec.map(_.getTriggerAction)).asUInt
1018 // exceptions
1019 val raiseException = csrio.exception.valid && !csrio.exception.bits.isInterrupt
1020 val hasInstrPageFault = csrio.exception.bits.uop.cf.exceptionVec(instrPageFault) && raiseException
1021 val hasLoadPageFault = csrio.exception.bits.uop.cf.exceptionVec(loadPageFault) && raiseException
1022 val hasStorePageFault = csrio.exception.bits.uop.cf.exceptionVec(storePageFault) && raiseException
1023 val hasStoreAddrMisaligned = csrio.exception.bits.uop.cf.exceptionVec(storeAddrMisaligned) && raiseException
1024 val hasLoadAddrMisaligned = csrio.exception.bits.uop.cf.exceptionVec(loadAddrMisaligned) && raiseException
1025 val hasInstrAccessFault = csrio.exception.bits.uop.cf.exceptionVec(instrAccessFault) && raiseException
1026 val hasLoadAccessFault = csrio.exception.bits.uop.cf.exceptionVec(loadAccessFault) && raiseException
1027 val hasStoreAccessFault = csrio.exception.bits.uop.cf.exceptionVec(storeAccessFault) && raiseException
1028 val hasbreakPoint = csrio.exception.bits.uop.cf.exceptionVec(breakPoint) && raiseException
1029 val hasSingleStep = csrio.exception.bits.uop.ctrl.singleStep && raiseException
1030 val hasTriggerHit = (csrio.exception.bits.uop.cf.trigger.hit) && raiseException
1141
1031
1142
1143 XSDebug(hasSingleStep, "Debug Mode: single step exception\n")
1032 XSDebug(hasSingleStep, "Debug Mode: single step exception\n")
1144 XSDebug(hasTriggerFire, p"Debug Mode: trigger fire, frontend hit vec ${Binary(csrio.exception.bits.trigger.frontendHit.asUInt)} " +
1145 p"backend hit vec ${Binary(csrio.exception.bits.trigger.backendHit.asUInt)}\n")
1033 XSDebug(hasTriggerHit, p"Debug Mode: trigger hit, is frontend? ${Binary(csrio.exception.bits.uop.cf.trigger.frontendHit.asUInt)} " +
1034 p"backend hit vec ${Binary(csrio.exception.bits.uop.cf.trigger.backendHit.asUInt)}\n")
1146
1035
1147 val hasExceptionVec = csrio.exception.bits.exceptionVec
1148 val regularExceptionNO = ExceptionNO.priorities.foldRight(0.U)((i: Int, sum: UInt) => Mux(hasExceptionVec(i), i.U, sum))
1149 val exceptionNO = Mux(hasSingleStep || hasTriggerFire, 3.U, regularExceptionNO)
1150 val causeNO = (hasIntr << (XLEN - 1)).asUInt | Mux(hasIntr, intrNO, exceptionNO)
1036 val raiseExceptionVec = csrio.exception.bits.uop.cf.exceptionVec
1037 val regularExceptionNO = ExceptionNO.priorities.foldRight(0.U)((i: Int, sum: UInt) => Mux(raiseExceptionVec(i), i.U, sum))
1038 val exceptionNO = Mux(hasSingleStep || hasTriggerHit, 3.U, regularExceptionNO)
1039 val causeNO = (raiseIntr << (XLEN-1)).asUInt | Mux(raiseIntr, intrNO, exceptionNO)
1151
1040
1041 val raiseExceptionIntr = csrio.exception.valid
1152
1042
1153 val hasExceptionIntr = csrio.exception.valid
1043 val raiseDebugExceptionIntr = !debugMode && (hasbreakPoint || raiseDebugIntr || hasSingleStep || hasTriggerHit && triggerAction) // TODO
1044 val ebreakEnterParkLoop = debugMode && raiseExceptionIntr
1154
1045
1155 val hasDebugEbreakException = hasBreakPoint && ebreakEnterDebugMode
1156 val hasDebugTriggerException = hasTriggerFire && triggerFireAction === TrigActionEnum.DEBUG_MODE
1157 val hasDebugException = hasDebugEbreakException || hasDebugTriggerException || hasSingleStep
1158 val hasDebugTrap = hasDebugException || hasDebugIntr
1159 val ebreakEnterParkLoop = debugMode && hasExceptionIntr
1160
1161 XSDebug(hasExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",
1162 dexceptionPC, intrNO, intrVec, exceptionNO, hasExceptionVec.asUInt
1046 XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",
1047 dexceptionPC, intrNO, intrVec, exceptionNO, raiseExceptionVec.asUInt
1163 )
1048 )
1164 XSDebug(hasExceptionIntr,
1049 XSDebug(raiseExceptionIntr,
1165 "pc %x mstatus %x mideleg %x medeleg %x mode %x\n",
1166 dexceptionPC,
1167 mstatus,
1168 mideleg,
1169 medeleg,
1170 priviledgeMode
1171 )
1172
1173 // mtval write logic
1174 // Due to timing reasons of memExceptionVAddr, we delay the write of mtval and stval
1175 val memExceptionAddr = SignExt(csrio.memExceptionVAddr, XLEN)
1176 val updateTval = VecInit(Seq(
1177 hasInstrPageFault,
1178 hasLoadPageFault,
1179 hasStorePageFault,
1180 hasInstrAccessFault,
1181 hasLoadAccessFault,
1182 hasStoreAccessFault,
1050 "pc %x mstatus %x mideleg %x medeleg %x mode %x\n",
1051 dexceptionPC,
1052 mstatus,
1053 mideleg,
1054 medeleg,
1055 priviledgeMode
1056 )
1057
1058 // mtval write logic
1059 // Due to timing reasons of memExceptionVAddr, we delay the write of mtval and stval
1060 val memExceptionAddr = SignExt(csrio.memExceptionVAddr, XLEN)
1061 val updateTval = VecInit(Seq(
1062 hasInstrPageFault,
1063 hasLoadPageFault,
1064 hasStorePageFault,
1065 hasInstrAccessFault,
1066 hasLoadAccessFault,
1067 hasStoreAccessFault,
1183 hasLoadAddrMisalign,
1184 hasStoreAddrMisalign
1068 hasLoadAddrMisaligned,
1069 hasStoreAddrMisaligned
1185 )).asUInt.orR
1186 when (RegNext(RegNext(updateTval))) {
1187 val tval = Mux(
1188 RegNext(RegNext(hasInstrPageFault || hasInstrAccessFault)),
1189 RegNext(RegNext(Mux(
1070 )).asUInt.orR
1071 when (RegNext(RegNext(updateTval))) {
1072 val tval = Mux(
1073 RegNext(RegNext(hasInstrPageFault || hasInstrAccessFault)),
1074 RegNext(RegNext(Mux(
1190 csrio.exception.bits.crossPageIPFFix,
1191 SignExt(csrio.exception.bits.pc + 2.U, XLEN),
1075 csrio.exception.bits.uop.cf.crossPageIPFFix,
1076 SignExt(csrio.exception.bits.uop.cf.pc + 2.U, XLEN),
1192 iexceptionPC
1193 ))),
1194 memExceptionAddr
1195 )
1196 when (RegNext(priviledgeMode === ModeM)) {
1197 mtval := tval
1198 }.otherwise {
1199 stval := tval
1200 }
1201 }
1202
1203 val debugTrapTarget = Mux(!isEbreak && debugMode, 0x38020808.U, 0x38020800.U) // 0x808 is when an exception occurs in debug mode prog buf exec
1077 iexceptionPC
1078 ))),
1079 memExceptionAddr
1080 )
1081 when (RegNext(priviledgeMode === ModeM)) {
1082 mtval := tval
1083 }.otherwise {
1084 stval := tval
1085 }
1086 }
1087
1088 val debugTrapTarget = Mux(!isEbreak && debugMode, 0x38020808.U, 0x38020800.U) // 0x808 is when an exception occurs in debug mode prog buf exec
1204 val deleg = Mux(hasIntr, mideleg , medeleg)
1089 val deleg = Mux(raiseIntr, mideleg , medeleg)
1205 // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
1206 val delegS = deleg(causeNO(3,0)) && (priviledgeMode < ModeM)
1090 // val delegS = ((deleg & (1 << (causeNO & 0xf))) != 0) && (priviledgeMode < ModeM);
1091 val delegS = deleg(causeNO(3,0)) && (priviledgeMode < ModeM)
1207 val clearTval = !updateTval || hasIntr
1092 val clearTval = !updateTval || raiseIntr
1093 val isXRet = io.in.valid && func === CSROpType.jmp && !isEcall && !isEbreak
1208
1209 // ctrl block will use theses later for flush
1210 val isXRetFlag = RegInit(false.B)
1094
1095 // ctrl block will use theses later for flush
1096 val isXRetFlag = RegInit(false.B)
1211 when (DelayN(io.flush.valid, 5)) {
1097 when (DelayN(io.redirectIn.valid, 5)) {
1212 isXRetFlag := false.B
1213 }.elsewhen (isXRet) {
1214 isXRetFlag := true.B
1215 }
1216 csrio.isXRet := isXRetFlag
1098 isXRetFlag := false.B
1099 }.elsewhen (isXRet) {
1100 isXRetFlag := true.B
1101 }
1102 csrio.isXRet := isXRetFlag
1217 private val retTargetReg = RegEnable(retTarget, isXRet && !illegalRetTarget)
1218 private val illegalXret = RegEnable(illegalMret || illegalSret || illegalSModeSret, isXRet)
1103 val retTargetReg = RegEnable(retTarget, isXRet)
1219
1104
1220 private val xtvec = Mux(delegS, stvec, mtvec)
1221 private val xtvecBase = xtvec(VAddrBits - 1, 2)
1222 // When MODE=Vectored, all synchronous exceptions into M/S mode
1223 // cause the pc to be set to the address in the BASE field, whereas
1224 // interrupts cause the pc to be set to the address in the BASE field
1225 // plus four times the interrupt cause number.
1226 private val pcFromXtvec = Cat(xtvecBase + Mux(xtvec(0) && hasIntr, causeNO(3, 0), 0.U), 0.U(2.W))
1227
1105 val tvec = Mux(delegS, stvec, mtvec)
1106 val tvecBase = tvec(VAddrBits - 1, 2)
1228 // XRet sends redirect instead of Flush and isXRetFlag is true.B before redirect.valid.
1229 // ROB sends exception at T0 while CSR receives at T2.
1230 // We add a RegNext here and trapTarget is valid at T3.
1107 // XRet sends redirect instead of Flush and isXRetFlag is true.B before redirect.valid.
1108 // ROB sends exception at T0 while CSR receives at T2.
1109 // We add a RegNext here and trapTarget is valid at T3.
1231 csrio.trapTarget := RegEnable(
1232 MuxCase(pcFromXtvec, Seq(
1233 (isXRetFlag && !illegalXret) -> retTargetReg,
1234 ((hasDebugTrap && !debugMode) || ebreakEnterParkLoop) -> debugTrapTarget
1235 )),
1236 isXRetFlag || csrio.exception.valid)
1110 csrio.trapTarget := RegEnable(Mux(isXRetFlag,
1111 retTargetReg,
1112 Mux(raiseDebugExceptionIntr || ebreakEnterParkLoop, debugTrapTarget,
1113 // When MODE=Vectored, all synchronous exceptions into M/S mode
1114 // cause the pc to be set to the address in the BASE field, whereas
1115 // interrupts cause the pc to be set to the address in the BASE field
1116 // plus four times the interrupt cause number.
1117 Cat(tvecBase + Mux(tvec(0) && raiseIntr, causeNO(3, 0), 0.U), 0.U(2.W))
1118 )), isXRetFlag || csrio.exception.valid)
1237
1119
1238 when(hasExceptionIntr) {
1120 when (raiseExceptionIntr) {
1239 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
1240 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1241 val dcsrNew = WireInit(dcsr.asTypeOf(new DcsrStruct))
1242 val debugModeNew = WireInit(debugMode)
1121 val mstatusOld = WireInit(mstatus.asTypeOf(new MstatusStruct))
1122 val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))
1123 val dcsrNew = WireInit(dcsr.asTypeOf(new DcsrStruct))
1124 val debugModeNew = WireInit(debugMode)
1243 when(hasDebugTrap && !debugMode) {
1244 import DcsrStruct._
1245 debugModeNew := true.B
1246 dcsrNew.prv := priviledgeMode
1247 priviledgeMode := ModeM
1248 when(hasDebugIntr) {
1125
1126 when (raiseDebugExceptionIntr) {
1127 when (raiseDebugIntr) {
1128 debugModeNew := true.B
1129 mstatusNew.mprv := false.B
1249 dpc := iexceptionPC
1130 dpc := iexceptionPC
1250 dcsrNew.cause := CAUSE_HALTREQ
1251 XSDebug(hasDebugIntr, "Debug Mode: Trap to %x at pc %x\n", debugTrapTarget, dpc)
1252 }.otherwise { // hasDebugException
1253 dpc := iexceptionPC // TODO: check it when hasSingleStep
1254 dcsrNew.cause := MuxCase(0.U, Seq(
1255 hasTriggerFire -> CAUSE_TRIGGER,
1256 hasBreakPoint -> CAUSE_HALTREQ,
1257 hasSingleStep -> CAUSE_STEP
1258 ))
1131 dcsrNew.cause := 3.U
1132 dcsrNew.prv := priviledgeMode
1133 priviledgeMode := ModeM
1134 XSDebug(raiseDebugIntr, "Debug Mode: Trap to %x at pc %x\n", debugTrapTarget, dpc)
1135 }.elsewhen ((hasbreakPoint || hasSingleStep) && !debugMode) {
1136 // ebreak or ss in running hart
1137 debugModeNew := true.B
1138 dpc := iexceptionPC
1139 dcsrNew.cause := Mux(hasTriggerHit, 2.U, Mux(hasbreakPoint, 1.U, 4.U))
1140 dcsrNew.prv := priviledgeMode // TODO
1141 priviledgeMode := ModeM
1142 mstatusNew.mprv := false.B
1259 }
1260 dcsr := dcsrNew.asUInt
1261 debugIntrEnable := false.B
1262 }.elsewhen (debugMode) {
1263 //do nothing
1264 }.elsewhen (delegS) {
1265 scause := causeNO
1266 sepc := Mux(hasInstrPageFault || hasInstrAccessFault, iexceptionPC, dexceptionPC)

--- 10 unchanged lines hidden (view full) ---

1277 mstatusNew.ie.m := false.B
1278 priviledgeMode := ModeM
1279 when (clearTval) { mtval := 0.U }
1280 }
1281 mstatus := mstatusNew.asUInt
1282 debugMode := debugModeNew
1283 }
1284
1143 }
1144 dcsr := dcsrNew.asUInt
1145 debugIntrEnable := false.B
1146 }.elsewhen (debugMode) {
1147 //do nothing
1148 }.elsewhen (delegS) {
1149 scause := causeNO
1150 sepc := Mux(hasInstrPageFault || hasInstrAccessFault, iexceptionPC, dexceptionPC)

--- 10 unchanged lines hidden (view full) ---

1161 mstatusNew.ie.m := false.B
1162 priviledgeMode := ModeM
1163 when (clearTval) { mtval := 0.U }
1164 }
1165 mstatus := mstatusNew.asUInt
1166 debugMode := debugModeNew
1167 }
1168
1285 XSDebug(hasExceptionIntr && delegS, "sepc is written!!! pc:%x\n", io.in.bits.data.pc.get)
1169 XSDebug(raiseExceptionIntr && delegS, "sepc is written!!! pc:%x\n", cfIn.pc)
1286
1287 // Distributed CSR update req
1288 //
1289 // For now we use it to implement customized cache op
1290 // It can be delayed if necessary
1291
1292 val delayedUpdate0 = DelayN(csrio.distributedUpdate(0), 2)
1293 val delayedUpdate1 = DelayN(csrio.distributedUpdate(1), 2)

--- 28 unchanged lines hidden (view full) ---

1322 // TODO: rewrite mepc and sepc using a struct-like style with the LSB always being 0
1323 when (RegNext(RegNext(reset.asBool) && !reset.asBool)) {
1324 mepc := Cat(mepc(XLEN - 1, 1), 0.U(1.W))
1325 sepc := Cat(sepc(XLEN - 1, 1), 0.U(1.W))
1326 }
1327
1328 def readWithScala(addr: Int): UInt = mapping(addr)._1
1329
1170
1171 // Distributed CSR update req
1172 //
1173 // For now we use it to implement customized cache op
1174 // It can be delayed if necessary
1175
1176 val delayedUpdate0 = DelayN(csrio.distributedUpdate(0), 2)
1177 val delayedUpdate1 = DelayN(csrio.distributedUpdate(1), 2)

--- 28 unchanged lines hidden (view full) ---

1206 // TODO: rewrite mepc and sepc using a struct-like style with the LSB always being 0
1207 when (RegNext(RegNext(reset.asBool) && !reset.asBool)) {
1208 mepc := Cat(mepc(XLEN - 1, 1), 0.U(1.W))
1209 sepc := Cat(sepc(XLEN - 1, 1), 0.U(1.W))
1210 }
1211
1212 def readWithScala(addr: Int): UInt = mapping(addr)._1
1213
1330 val difftestIntrNO = Mux(hasIntr, causeNO, 0.U)
1214 val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
1331
1332 // Always instantiate basic difftest modules.
1333 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1334 val difftest = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true)
1335 difftest.coreid := csrio.hartId
1336 difftest.valid := csrio.exception.valid
1215
1216 // Always instantiate basic difftest modules.
1217 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1218 val difftest = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true)
1219 difftest.coreid := csrio.hartId
1220 difftest.valid := csrio.exception.valid
1337 difftest.interrupt := Mux(hasIntr, causeNO, 0.U)
1338 difftest.exception := Mux(hasException, causeNO, 0.U)
1221 difftest.interrupt := Mux(raiseIntr, causeNO, 0.U)
1222 difftest.exception := Mux(raiseException, causeNO, 0.U)
1339 difftest.exceptionPC := dexceptionPC
1340 if (env.EnableDifftest) {
1223 difftest.exceptionPC := dexceptionPC
1224 if (env.EnableDifftest) {
1341 difftest.exceptionInst := csrio.exception.bits.instr
1225 difftest.exceptionInst := csrio.exception.bits.uop.cf.instr
1342 }
1343 }
1344
1345 // Always instantiate basic difftest modules.
1346 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1347 val difftest = DifftestModule(new DiffCSRState)
1348 difftest.coreid := csrio.hartId
1349 difftest.priviledgeMode := priviledgeMode

--- 17 unchanged lines hidden (view full) ---

1367 }
1368
1369 if(env.AlwaysBasicDiff || env.EnableDifftest) {
1370 val difftest = DifftestModule(new DiffDebugMode)
1371 difftest.coreid := csrio.hartId
1372 difftest.debugMode := debugMode
1373 difftest.dcsr := dcsr
1374 difftest.dpc := dpc
1226 }
1227 }
1228
1229 // Always instantiate basic difftest modules.
1230 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1231 val difftest = DifftestModule(new DiffCSRState)
1232 difftest.coreid := csrio.hartId
1233 difftest.priviledgeMode := priviledgeMode

--- 17 unchanged lines hidden (view full) ---

1251 }
1252
1253 if(env.AlwaysBasicDiff || env.EnableDifftest) {
1254 val difftest = DifftestModule(new DiffDebugMode)
1255 difftest.coreid := csrio.hartId
1256 difftest.debugMode := debugMode
1257 difftest.dcsr := dcsr
1258 difftest.dpc := dpc
1375 difftest.dscratch0 := dscratch0
1259 difftest.dscratch0 := dscratch
1376 difftest.dscratch1 := dscratch1
1377 }
1260 difftest.dscratch1 := dscratch1
1261 }
1378
1379 if (env.AlwaysBasicDiff || env.EnableDifftest) {
1380 val difftest = DifftestModule(new DiffVecCSRState)
1381 difftest.coreid := csrio.hartId
1382 difftest.vstart := vstart
1383 difftest.vxsat := vcsr.asTypeOf(new VcsrStruct).vxsat
1384 difftest.vxrm := vcsr.asTypeOf(new VcsrStruct).vxrm
1385 difftest.vcsr := vcsr
1386 difftest.vl := vl
1387 difftest.vtype := vtype
1388 difftest.vlenb := vlenb
1389 }
1390}
1391
1392class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst {
1393 val io = IO(new Bundle {
1394 val distribute_csr = Flipped(new DistributedCSRIO())
1395 val hpmevent = Output(Vec(29, UInt(XLEN.W)))
1396 })
1397

--- 19 unchanged lines hidden --- 		1262}
1263
1264class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst {
1265 val io = IO(new Bundle {
1266 val distribute_csr = Flipped(new DistributedCSRIO())
1267 val hpmevent = Output(Vec(29, UInt(XLEN.W)))
1268 })
1269

--- 19 unchanged lines hidden ---