Bku.scala (6a35d972887e2dbfc0705b0fa8b979b13df0f3d1) Bku.scala (8891a219bbc84f568e1d134854d8d5ed86d6d560)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utility.{LookupTreeDefault, ParallelMux, ParallelXOR, SignExt, ZeroExt}
23import utils.{XSDebug, XSError}
24import xiangshan._
25import xiangshan.backend.fu.util._
26
20import chisel3._
21import chisel3.util._
22import utility.{LookupTreeDefault, ParallelMux, ParallelXOR, SignExt, ZeroExt}
23import utils.{XSDebug, XSError}
24import xiangshan._
25import xiangshan.backend.fu.util._
26
27
28
29
27class CountModule(implicit p: Parameters) extends XSModule {
28 val io = IO(new Bundle() {
29 val src = Input(UInt(XLEN.W))
30 val func = Input(UInt())
31 val regEnable = Input(Bool())
32 val out = Output(UInt(XLEN.W))
33 })
34

--- 278 unchanged lines hidden (view full) ---

313 blockCipherModule.io.src(0) := src1
314 blockCipherModule.io.src(1) := src2
315 blockCipherModule.io.func := func
316 blockCipherModule.io.regEnable := io.regEnable
317
318 io.out := Mux(funcReg(4), hashModule.io.out, blockCipherModule.io.out)
319}
320
30class CountModule(implicit p: Parameters) extends XSModule {
31 val io = IO(new Bundle() {
32 val src = Input(UInt(XLEN.W))
33 val func = Input(UInt())
34 val regEnable = Input(Bool())
35 val out = Output(UInt(XLEN.W))
36 })
37

--- 278 unchanged lines hidden (view full) ---

316 blockCipherModule.io.src(0) := src1
317 blockCipherModule.io.src(1) := src2
318 blockCipherModule.io.func := func
319 blockCipherModule.io.regEnable := io.regEnable
320
321 io.out := Mux(funcReg(4), hashModule.io.out, blockCipherModule.io.out)
322}
323
321class Bku(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) with HasPipelineReg {
324class Bku(implicit p: Parameters) extends FunctionUnit with HasPipelineReg {
322
323 override def latency = 2
324
325 val (src1, src2, func) = (
325
326 override def latency = 2
327
328 val (src1, src2, func) = (
326 io.in.bits.data.src(0),
327 io.in.bits.data.src(1),
328 io.in.bits.ctrl.fuOpType
329 io.in.bits.src(0),
330 io.in.bits.src(1),
331 io.in.bits.uop.ctrl.fuOpType
329 )
330
331 val countModule = Module(new CountModule)
332 countModule.io.src := src1
333 countModule.io.func := func
334 countModule.io.regEnable := regEnable(1)
335
336 val clmulModule = Module(new ClmulModule)

--- 11 unchanged lines hidden (view full) ---

348 val cryptoModule = Module(new CryptoModule)
349 cryptoModule.io.src(0) := src1
350 cryptoModule.io.src(1) := src2
351 cryptoModule.io.func := func
352 cryptoModule.io.regEnable := regEnable(1)
353
354
355 // CountModule, ClmulModule, MiscModule, and CryptoModule have a latency of 1 cycle
332 )
333
334 val countModule = Module(new CountModule)
335 countModule.io.src := src1
336 countModule.io.func := func
337 countModule.io.regEnable := regEnable(1)
338
339 val clmulModule = Module(new ClmulModule)

--- 11 unchanged lines hidden (view full) ---

351 val cryptoModule = Module(new CryptoModule)
352 cryptoModule.io.src(0) := src1
353 cryptoModule.io.src(1) := src2
354 cryptoModule.io.func := func
355 cryptoModule.io.regEnable := regEnable(1)
356
357
358 // CountModule, ClmulModule, MiscModule, and CryptoModule have a latency of 1 cycle
356 val funcReg = RegEnable(func, io.in.fire)
359 val funcReg = uopVec(1).ctrl.fuOpType
357 val result = Mux(funcReg(5), cryptoModule.io.out,
358 Mux(funcReg(3), countModule.io.out,
359 Mux(funcReg(2),miscModule.io.out, clmulModule.io.out)))
360
360 val result = Mux(funcReg(5), cryptoModule.io.out,
361 Mux(funcReg(3), countModule.io.out,
362 Mux(funcReg(2),miscModule.io.out, clmulModule.io.out)))
363
361 io.out.bits.res.data := RegEnable(result, regEnable(2))
362 // connectNonPipedCtrlSingal
364 io.out.bits.data := RegEnable(result, regEnable(2))
363}
365}