| Backend.scala (f9f1abd72b0116a2b8cc02eb47a958861191c445) | Backend.scala (6810d1e8e7c0789e9f50ee6bdd52010b8ce506ef) |
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| 1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ --- 503 unchanged lines hidden (view full) --- 512 // params alias 513 private val LoadQueueSize = VirtualLoadQueueSize 514 // In/Out // Todo: split it into one-direction bundle 515 val lsqEnqIO = Flipped(new LsqEnqIO) 516 val robLsqIO = new RobLsqIO 517 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 518 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 519 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) | 1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ --- 503 unchanged lines hidden (view full) --- 512 // params alias 513 private val LoadQueueSize = VirtualLoadQueueSize 514 // In/Out // Todo: split it into one-direction bundle 515 val lsqEnqIO = Flipped(new LsqEnqIO) 516 val robLsqIO = new RobLsqIO 517 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 518 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 519 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) |
| 520 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) | 520 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) |
| 521 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 522 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 523 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 524 // Input 525 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 526 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 527 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 528 // 0: Hybrid load, 1: Hybrid store --- 15 unchanged lines hidden (view full) --- 544 545 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 546 val stIssuePtr = Input(new SqPtr()) 547 548 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 549 550 val debugLS = Flipped(Output(new DebugLSIO)) 551 | 521 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 522 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 523 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 524 // Input 525 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 526 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 527 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 528 // 0: Hybrid load, 1: Hybrid store --- 15 unchanged lines hidden (view full) --- 544 545 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 546 val stIssuePtr = Input(new SqPtr()) 547 548 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 549 550 val debugLS = Flipped(Output(new DebugLSIO)) 551 |
| 552 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) | 552 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) |
| 553 // Output 554 val redirect = ValidIO(new Redirect) // rob flush MemBlock 555 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 556 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 557 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 558 val issueHya = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 559 // hybrid unit store data use this 560 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(isVector = true)))) --- 67 unchanged lines hidden --- | 553 // Output 554 val redirect = ValidIO(new Redirect) // rob flush MemBlock 555 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 556 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 557 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 558 val issueHya = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 559 // hybrid unit store data use this 560 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(isVector = true)))) --- 67 unchanged lines hidden --- |