| Backend.scala (bb411583d67d3e26be9ec97718ea0fd2b9939721) | Backend.scala (518d86588c9b2d06b514bf268da5d10fc897f3e8) |
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| 1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ --- 189 unchanged lines hidden (view full) --- 198 dispatch.io.redirect <> redirect 199 dispatch.io.fromRename <> rename.io.out 200 201 roq.io.brqRedirect <> brq.io.redirect 202 roq.io.dp1Req <> dispatch.io.toRoq 203 dispatch.io.roqIdxs <> roq.io.roqIdxs 204 io.mem.dp1Req <> dispatch.io.toMoq 205 dispatch.io.moqIdxs <> io.mem.moqIdxs | 1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ --- 189 unchanged lines hidden (view full) --- 198 dispatch.io.redirect <> redirect 199 dispatch.io.fromRename <> rename.io.out 200 201 roq.io.brqRedirect <> brq.io.redirect 202 roq.io.dp1Req <> dispatch.io.toRoq 203 dispatch.io.roqIdxs <> roq.io.roqIdxs 204 io.mem.dp1Req <> dispatch.io.toMoq 205 dispatch.io.moqIdxs <> io.mem.moqIdxs |
| 206 dispatch.io.commits <> roq.io.commits |
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| 206 207 intRf.io.readPorts <> dispatch.io.readIntRf 208 fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf) 209 memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf) 210 211 val wbIntIdx = exuConfigs.zipWithIndex.filter(_._1.writeIntRf).map(_._2) 212 val wbFpIdx = exuConfigs.zipWithIndex.filter(_._1.writeFpRf).map(_._2) 213 --- 54 unchanged lines hidden --- | 207 208 intRf.io.readPorts <> dispatch.io.readIntRf 209 fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf) 210 memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf) 211 212 val wbIntIdx = exuConfigs.zipWithIndex.filter(_._1.writeIntRf).map(_._2) 213 val wbFpIdx = exuConfigs.zipWithIndex.filter(_._1.writeFpRf).map(_._2) 214 --- 54 unchanged lines hidden --- |