Backend.scala (7edcfc93d3ce141e6d7c350af4013c25e3dbdbef) Backend.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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58 val inner = LazyModule(new BackendInlined(params))
59 lazy val module = new BackendImp(this)
60}
61
62class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) {
63 val io = IO(new BackendIO()(p, wrapper.params))
64 io <> wrapper.inner.module.io
65 if (p(DebugOptionsKey).ResetGen) {
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 49 unchanged lines hidden (view full) ---

58 val inner = LazyModule(new BackendInlined(params))
59 lazy val module = new BackendImp(this)
60}
61
62class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) {
63 val io = IO(new BackendIO()(p, wrapper.params))
64 io <> wrapper.inner.module.io
65 if (p(DebugOptionsKey).ResetGen) {
66 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false)
66 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false, io.dft_reset)
67 }
68}
69
70class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule
71 with HasXSParameter {
72
73 override def shouldBeInlined: Boolean = true
74

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858
859 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob
860 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore
861
862 io.debugRolling := ctrlBlock.io.debugRolling
863
864 io.topDownInfo.noUopsIssued := RegNext(dataPath.io.topDownInfo.noUopsIssued)
865
67 }
68}
69
70class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule
71 with HasXSParameter {
72
73 override def shouldBeInlined: Boolean = true
74

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858
859 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob
860 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore
861
862 io.debugRolling := ctrlBlock.io.debugRolling
863
864 io.topDownInfo.noUopsIssued := RegNext(dataPath.io.topDownInfo.noUopsIssued)
865
866 private val cg = ClockGate.genTeSrc
867 dontTouch(cg)
868 if(hasMbist) {
869 cg.cgen := io.dft_cgen.get
870 } else {
871 cg.cgen := false.B
872 }
873
866 if(backendParams.debugEn) {
867 dontTouch(memScheduler.io)
868 dontTouch(dataPath.io.toMemExu)
869 dontTouch(wbDataPath.io.fromMemExu)
870 }
871
872 // reset tree
873 if (p(DebugOptionsKey).ResetGen) {

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888 ModuleNode(wbFuBusyTable),
889 ResetGenNode(Seq(
890 ModuleNode(ctrlBlock),
891 // ResetGenNode(Seq(
892 CellNode(io.frontendReset)
893 // ))
894 ))
895 ))
874 if(backendParams.debugEn) {
875 dontTouch(memScheduler.io)
876 dontTouch(dataPath.io.toMemExu)
877 dontTouch(wbDataPath.io.fromMemExu)
878 }
879
880 // reset tree
881 if (p(DebugOptionsKey).ResetGen) {

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896 ModuleNode(wbFuBusyTable),
897 ResetGenNode(Seq(
898 ModuleNode(ctrlBlock),
899 // ResetGenNode(Seq(
900 CellNode(io.frontendReset)
901 // ))
902 ))
903 ))
896 ResetGen(leftResetTree, reset, sim = false)
897 ResetGen(rightResetTree, reset, sim = false)
904 ResetGen(leftResetTree, reset, sim = false, io.dft_reset)
905 ResetGen(rightResetTree, reset, sim = false, io.dft_reset)
898 } else {
899 io.frontendReset := DontCare
900 }
901
902 // perf events
903 val pfevent = Module(new PFEvent)
904 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr)
905 val csrevents = pfevent.io.hpmevent.slice(8,16)

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1072 val csrCustomCtrl = Output(new CustomCSRCtrlIO)
1073
1074 val debugTopDown = new Bundle {
1075 val fromRob = new RobCoreTopDownIO
1076 val fromCore = new CoreDispatchTopDownIO
1077 }
1078 val debugRolling = new RobDebugRollingIO
1079 val topDownInfo = new TopDownInfo
906 } else {
907 io.frontendReset := DontCare
908 }
909
910 // perf events
911 val pfevent = Module(new PFEvent)
912 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr)
913 val csrevents = pfevent.io.hpmevent.slice(8,16)

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1080 val csrCustomCtrl = Output(new CustomCSRCtrlIO)
1081
1082 val debugTopDown = new Bundle {
1083 val fromRob = new RobCoreTopDownIO
1084 val fromCore = new CoreDispatchTopDownIO
1085 }
1086 val debugRolling = new RobDebugRollingIO
1087 val topDownInfo = new TopDownInfo
1088 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals)) else None
1089 val dft_cgen = if(hasMbist) Some(Input(Bool())) else None
1080}
1090}