| XSTile.scala (cac098b457095a5d9bdf69be79941e4b41de996b) | XSTile.scala (59239bc96a73f430bbcce1d2e7f46fb72ed68048) |
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| 1package xiangshan 2 3import chisel3._ 4import chipsalliance.rocketchip.config.{Config, Parameters} 5import chisel3.util.{Valid, ValidIO} 6import freechips.rocketchip.diplomacy.{BundleBridgeSink, LazyModule, LazyModuleImp, LazyModuleImpLike} 7import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode 8import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple} 9import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 10import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLNode, TLTempNode, TLXbar} 11import huancun.debug.TLLogger 12import huancun.{HCCacheParamsKey, HuanCun} 13import system.HasSoCParameter 14import top.BusPerfMonitor | 1package xiangshan 2 3import chisel3._ 4import chipsalliance.rocketchip.config.{Config, Parameters} 5import chisel3.util.{Valid, ValidIO} 6import freechips.rocketchip.diplomacy.{BundleBridgeSink, LazyModule, LazyModuleImp, LazyModuleImpLike} 7import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode 8import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple} 9import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 10import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLNode, TLTempNode, TLXbar} 11import huancun.debug.TLLogger 12import huancun.{HCCacheParamsKey, HuanCun} 13import system.HasSoCParameter 14import top.BusPerfMonitor |
| 15import utils.{ResetGen, TLEdgeBuffer} | 15import utils.{ResetGen, TLClientsMerger, TLEdgeBuffer} |
| 16 17class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 18 val paddr = Valid(UInt(soc.PAddrBits.W)) 19 // for now, we only detect ecc 20 val ecc_error = Valid(Bool()) 21} 22 23class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { --- 29 unchanged lines hidden (view full) --- 53 val i_mmio_port = TLTempNode() 54 val d_mmio_port = TLTempNode() 55 56 busPMU := l1d_logger 57 l1_xbar :=* busPMU 58 59 l2_binder match { 60 case Some(binder) => | 16 17class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 18 val paddr = Valid(UInt(soc.PAddrBits.W)) 19 // for now, we only detect ecc 20 val ecc_error = Valid(Bool()) 21} 22 23class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { --- 29 unchanged lines hidden (view full) --- 53 val i_mmio_port = TLTempNode() 54 val d_mmio_port = TLTempNode() 55 56 busPMU := l1d_logger 57 l1_xbar :=* busPMU 58 59 l2_binder match { 60 case Some(binder) => |
| 61 memory_port :=* TLEdgeBuffer(_ => true, Some("l2_to_l3_buffer")) :=* binder | 61 memory_port := TLBuffer() := TLClientsMerger() := TLXbar() :=* binder |
| 62 case None => 63 memory_port := l1_xbar 64 } 65 66 mmio_xbar := TLBuffer() := i_mmio_port 67 mmio_xbar := TLBuffer() := d_mmio_port 68 beu.node := TLBuffer() := mmio_xbar 69 --- 83 unchanged lines hidden --- | 62 case None => 63 memory_port := l1_xbar 64 } 65 66 mmio_xbar := TLBuffer() := i_mmio_port 67 mmio_xbar := TLBuffer() := d_mmio_port 68 beu.node := TLBuffer() := mmio_xbar 69 --- 83 unchanged lines hidden --- |