XSTile.scala (a1c09046dd828e40a255a90bebb9a9b6362791d5) XSTile.scala (15ee59e46c33fe60e4408711f9ea0a6078d50510)
1package xiangshan
2
3import chisel3._
4import chipsalliance.rocketchip.config.{Config, Parameters}
5import chisel3.util.{Valid, ValidIO}
6import freechips.rocketchip.diplomacy._
7import freechips.rocketchip.interrupts._
8import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
9import freechips.rocketchip.tilelink._
10import huancun.debug.TLLogger
1package xiangshan
2
3import chisel3._
4import chipsalliance.rocketchip.config.{Config, Parameters}
5import chisel3.util.{Valid, ValidIO}
6import freechips.rocketchip.diplomacy._
7import freechips.rocketchip.interrupts._
8import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
9import freechips.rocketchip.tilelink._
10import huancun.debug.TLLogger
11import huancun.{HCCacheParamsKey, HuanCun}
11import coupledL2.{L2ParamKey, CoupledL2}
12import system.HasSoCParameter
13import top.BusPerfMonitor
14import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer}
15
16class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
17 val ecc_error = Valid(UInt(soc.PAddrBits.W))
18}
19

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74
75class XSTile()(implicit p: Parameters) extends LazyModule
76 with HasXSParameter
77 with HasSoCParameter
78{
79 private val core = LazyModule(new XSCore())
80 private val misc = LazyModule(new XSTileMisc())
81 private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
12import system.HasSoCParameter
13import top.BusPerfMonitor
14import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer}
15
16class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
17 val ecc_error = Valid(UInt(soc.PAddrBits.W))
18}
19

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74
75class XSTile()(implicit p: Parameters) extends LazyModule
76 with HasXSParameter
77 with HasSoCParameter
78{
79 private val core = LazyModule(new XSCore())
80 private val misc = LazyModule(new XSTileMisc())
81 private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
82 LazyModule(new HuanCun()(new Config((_, _, _) => {
83 case HCCacheParamsKey => l2param.copy(enableTopDown = env.EnableTopDown)
82 LazyModule(new CoupledL2()(new Config((_, _, _) => {
83 case L2ParamKey => l2param
84 })))
85 )
86
87 // public ports
88 val memory_port = misc.memory_port
89 val uncache = misc.mmio_port
90 val clint_int_sink = core.clint_int_sink
91 val plic_int_sink = core.plic_int_sink

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135
136 dontTouch(io.hartId)
137
138 val core_soft_rst = core_reset_sink.in.head._1
139
140 core.module.io.hartId := io.hartId
141 core.module.io.reset_vector := DelayN(io.reset_vector, 5)
142 io.cpu_halt := core.module.io.cpu_halt
84 })))
85 )
86
87 // public ports
88 val memory_port = misc.memory_port
89 val uncache = misc.mmio_port
90 val clint_int_sink = core.clint_int_sink
91 val plic_int_sink = core.plic_int_sink

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135
136 dontTouch(io.hartId)
137
138 val core_soft_rst = core_reset_sink.in.head._1
139
140 core.module.io.hartId := io.hartId
141 core.module.io.reset_vector := DelayN(io.reset_vector, 5)
142 io.cpu_halt := core.module.io.cpu_halt
143 if(l2cache.isDefined){
144 core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2)
143 if (l2cache.isDefined) {
144 // TODO: add perfEvents of L2
145 // core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2)
145 }
146 else {
147 core.module.io.perfEvents <> DontCare
148 }
149
150 misc.module.beu_errors.icache <> core.module.io.beu_errors.icache
151 misc.module.beu_errors.dcache <> core.module.io.beu_errors.dcache
146 }
147 else {
148 core.module.io.perfEvents <> DontCare
149 }
150
151 misc.module.beu_errors.icache <> core.module.io.beu_errors.icache
152 misc.module.beu_errors.dcache <> core.module.io.beu_errors.dcache
152 if(l2cache.isDefined){
153 misc.module.beu_errors.l2.ecc_error.valid := l2cache.get.module.io.ecc_error.valid
154 misc.module.beu_errors.l2.ecc_error.bits := l2cache.get.module.io.ecc_error.bits
153 if (l2cache.isDefined) {
154 // TODO: add ECC interface of L2
155 // misc.module.beu_errors.l2.ecc_error.valid := l2cache.get.module.io.ecc_error.valid
156 // misc.module.beu_errors.l2.ecc_error.bits := l2cache.get.module.io.ecc_error.bits
157 misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
155 } else {
156 misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
157 }
158
159 // Modules are reset one by one
160 // io_reset ----
161 // |
162 // v
163 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
164 val resetChain = Seq(
165 Seq(misc.module, core.module) ++
166 l1d_to_l2_bufferOpt.map(_.module) ++
167 l2cache.map(_.module)
168 )
169 ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
170 }
171}
158 } else {
159 misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
160 }
161
162 // Modules are reset one by one
163 // io_reset ----
164 // |
165 // v
166 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
167 val resetChain = Seq(
168 Seq(misc.module, core.module) ++
169 l1d_to_l2_bufferOpt.map(_.module) ++
170 l2cache.map(_.module)
171 )
172 ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
173 }
174}