XSTile.scala (67fcf090b92eeb68aff35affc52316c799043ffb) XSTile.scala (a1c09046dd828e40a255a90bebb9a9b6362791d5)
1package xiangshan
2
1package xiangshan
2
3import chipsalliance.rocketchip.config.{Config, Parameters}
4import chisel3._
3import chisel3._
4import chipsalliance.rocketchip.config.{Config, Parameters}
5import chisel3.util.{Valid, ValidIO}
6import freechips.rocketchip.diplomacy._
7import freechips.rocketchip.interrupts._
8import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
9import freechips.rocketchip.tilelink._
10import huancun.debug.TLLogger
11import huancun.{HCCacheParamsKey, HuanCun}
12import system.HasSoCParameter
13import top.BusPerfMonitor
5import chisel3.util.{Valid, ValidIO}
6import freechips.rocketchip.diplomacy._
7import freechips.rocketchip.interrupts._
8import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
9import freechips.rocketchip.tilelink._
10import huancun.debug.TLLogger
11import huancun.{HCCacheParamsKey, HuanCun}
12import system.HasSoCParameter
13import top.BusPerfMonitor
14import utility.{DelayN, ResetGen, TLClientsMerger}
14import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer}
15
16class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
17 val ecc_error = Valid(UInt(soc.PAddrBits.W))
18}
19
20class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
21 val icache = new L1BusErrorUnitInfo
22 val dcache = new L1BusErrorUnitInfo

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71 beu.module.io.errors <> beu_errors
72 }
73}
74
75class XSTile()(implicit p: Parameters) extends LazyModule
76 with HasXSParameter
77 with HasSoCParameter
78{
15
16class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
17 val ecc_error = Valid(UInt(soc.PAddrBits.W))
18}
19
20class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
21 val icache = new L1BusErrorUnitInfo
22 val dcache = new L1BusErrorUnitInfo

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71 beu.module.io.errors <> beu_errors
72 }
73}
74
75class XSTile()(implicit p: Parameters) extends LazyModule
76 with HasXSParameter
77 with HasSoCParameter
78{
79 val core = LazyModule(new XSCore())
79 private val core = LazyModule(new XSCore())
80 private val misc = LazyModule(new XSTileMisc())
81 private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
82 LazyModule(new HuanCun()(new Config((_, _, _) => {
83 case HCCacheParamsKey => l2param.copy(enableTopDown = env.EnableTopDown)
84 })))
85 )
86
87 // public ports

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103 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
104 buffers.zipWithIndex.foreach{ case (b, i) => {
105 b.suggestName(s"${n}_${i}")
106 }}
107 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
108 (buffers, node)
109 }
110
80 private val misc = LazyModule(new XSTileMisc())
81 private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
82 LazyModule(new HuanCun()(new Config((_, _, _) => {
83 case HCCacheParamsKey => l2param.copy(enableTopDown = env.EnableTopDown)
84 })))
85 )
86
87 // public ports

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103 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
104 buffers.zipWithIndex.foreach{ case (b, i) => {
105 b.suggestName(s"${n}_${i}")
106 }}
107 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
108 (buffers, node)
109 }
110
111 val (l1i_to_l2_buffers, l1i_to_l2_buf_node) = chainBuffer(3, "l1i_to_l2_buffer")
112 misc.busPMU :=
113 TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
114 l1i_to_l2_buf_node :=
115 core.frontend.icache.clientNode
111 misc.busPMU := TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) := core.frontend.icache.clientNode
112 if (!coreParams.softPTW) {
113 misc.busPMU := TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) := core.ptw_to_l2_buffer.node
114 }
116
115
117 val ptw_to_l2_buffers = if (!coreParams.softPTW) {
118 val (buffers, buf_node) = chainBuffer(5, "ptw_to_l2_buffer")
119 misc.busPMU :=
120 TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
121 buf_node :=
122 core.ptw_to_l2_buffer.node
123 buffers
124 } else Seq()
125
126 l2cache match {
127 case Some(l2) =>
116 l2cache match {
117 case Some(l2) =>
128 misc.l2_binder.get :*= l2.node :*= TLBuffer() :*= TLBuffer() :*= misc.l1_xbar
118 misc.l2_binder.get :*= l2.node :*= misc.l1_xbar
129 l2.pf_recv_node.map(recv => {
130 println("Connecting L1 prefetcher to L2!")
131 recv := core.memBlock.pf_sender_opt.get
132 })
133 case None =>
134 }
135
136 misc.i_mmio_port := core.frontend.instrUncache.clientNode

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168
169 // Modules are reset one by one
170 // io_reset ----
171 // |
172 // v
173 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
174 val resetChain = Seq(
175 Seq(misc.module, core.module) ++
119 l2.pf_recv_node.map(recv => {
120 println("Connecting L1 prefetcher to L2!")
121 recv := core.memBlock.pf_sender_opt.get
122 })
123 case None =>
124 }
125
126 misc.i_mmio_port := core.frontend.instrUncache.clientNode

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158
159 // Modules are reset one by one
160 // io_reset ----
161 // |
162 // v
163 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
164 val resetChain = Seq(
165 Seq(misc.module, core.module) ++
176 l1i_to_l2_buffers.map(_.module.asInstanceOf[MultiIOModule]) ++
177 ptw_to_l2_buffers.map(_.module.asInstanceOf[MultiIOModule]) ++
178 l1d_to_l2_bufferOpt.map(_.module) ++
179 l2cache.map(_.module)
180 )
181 ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
182 }
183}
166 l1d_to_l2_bufferOpt.map(_.module) ++
167 l2cache.map(_.module)
168 )
169 ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
170 }
171}