XSTile.scala (4a699e275a42daaf03e4f014bad0bb16d893e6ff) XSTile.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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21import chisel3.util.{Valid, ValidIO, log2Up}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
27import device.MsiInfoBundle
28import system.HasSoCParameter
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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21import chisel3.util.{Valid, ValidIO, log2Up}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
27import device.MsiInfoBundle
28import system.HasSoCParameter
29import top.{BusPerfMonitor, ArgParser, Generator}
30import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters}
29import top.{ArgParser, BusPerfMonitor, Generator}
30import utility.{ChiselDB, Constantin, DFTResetSignals, DelayN, FileRegisters, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger}
31import coupledL2.EnableCHI
32import coupledL2.tl2chi.PortIO
31import coupledL2.EnableCHI
32import coupledL2.tl2chi.PortIO
33import utility.sram.SramBroadcastBundle
33import xiangshan.backend.trace.TraceCoreInterface
34
35class XSTile()(implicit p: Parameters) extends LazyModule
36 with HasXSParameter
37 with HasSoCParameter
38{
39 override def shouldBeInlined: Boolean = false
40 val core = LazyModule(new XSCore())

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110 val debugTopDown = new Bundle {
111 val robHeadPaddr = Valid(UInt(PAddrBits.W))
112 val l3MissMatch = Input(Bool())
113 }
114 val l3Miss = Input(Bool())
115 val chi = if (enableCHI) Some(new PortIO) else None
116 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
117 val clintTime = Input(ValidIO(UInt(64.W)))
34import xiangshan.backend.trace.TraceCoreInterface
35
36class XSTile()(implicit p: Parameters) extends LazyModule
37 with HasXSParameter
38 with HasSoCParameter
39{
40 override def shouldBeInlined: Boolean = false
41 val core = LazyModule(new XSCore())

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111 val debugTopDown = new Bundle {
112 val robHeadPaddr = Valid(UInt(PAddrBits.W))
113 val l3MissMatch = Input(Bool())
114 }
115 val l3Miss = Input(Bool())
116 val chi = if (enableCHI) Some(new PortIO) else None
117 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
118 val clintTime = Input(ValidIO(UInt(64.W)))
119 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None
120 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None
118 })
119
120 dontTouch(io.hartId)
121 dontTouch(io.msiInfo)
122 dontTouch(io.cpu_poff)
123 if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
124
125 val core_soft_rst = core_reset_sink.in.head._1 // unused

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145 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
146 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache
147
148 //lower power
149 l2top.module.io.l2_flush_en := core.module.io.l2_flush_en
150 core.module.io.l2_flush_done := l2top.module.io.l2_flush_done
151 io.cpu_poff := l2top.module.io.cpu_poff.toTile
152 l2top.module.io.cpu_poff.fromCore := core.module.io.power_down_en
121 })
122
123 dontTouch(io.hartId)
124 dontTouch(io.msiInfo)
125 dontTouch(io.cpu_poff)
126 if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
127
128 val core_soft_rst = core_reset_sink.in.head._1 // unused

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148 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
149 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache
150
151 //lower power
152 l2top.module.io.l2_flush_en := core.module.io.l2_flush_en
153 core.module.io.l2_flush_done := l2top.module.io.l2_flush_done
154 io.cpu_poff := l2top.module.io.cpu_poff.toTile
155 l2top.module.io.cpu_poff.fromCore := core.module.io.power_down_en
156 l2top.module.io.dft.zip(io.dft).foreach({case(a, b) => a := b})
157 l2top.module.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b})
158 core.module.io.dft.zip(l2top.module.io.dft_out).foreach({case(a, b) => a := b})
159 core.module.io.dft_reset.zip(l2top.module.io.dft_reset_out).foreach({case(a, b) => a := b})
160
153 if (enableL2) {
154 // TODO: add ECC interface of L2
155 l2top.module.io.pfCtrlFromCore := core.module.io.l2PfCtrl
156
157 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
158 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
159 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
160 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid

--- 44 unchanged lines hidden --- 		161 if (enableL2) {
162 // TODO: add ECC interface of L2
163 l2top.module.io.pfCtrlFromCore := core.module.io.l2PfCtrl
164
165 l2top.module.io.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.io.beu_errors.l2)
166 core.module.io.l2_hint.bits.sourceId := l2top.module.io.l2_hint.bits.sourceId
167 core.module.io.l2_hint.bits.isKeyword := l2top.module.io.l2_hint.bits.isKeyword
168 core.module.io.l2_hint.valid := l2top.module.io.l2_hint.valid

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