XSTile.scala (42cb64260d34f2b47839d26c7af8b31eef9031c9) XSTile.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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19import org.chipsalliance.cde.config.{Config, Parameters}
20import chisel3._
21import chisel3.util.{Valid, ValidIO, log2Up}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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19import org.chipsalliance.cde.config.{Config, Parameters}
20import chisel3._
21import chisel3.util.{Valid, ValidIO, log2Up}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import freechips.rocketchip.amba.axi4._
27import device.MsiInfoBundle
28import system.HasSoCParameter
29import top.{ArgParser, BusPerfMonitor, Generator}
30import utility.{ChiselDB, Constantin, DFTResetSignals, DelayN, FileRegisters, IntBuffer, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger}
31import utility.sram.SramMbistBundle
32import coupledL2.EnableCHI
33import coupledL2.tl2chi.PortIO
34import xiangshan.backend.trace.TraceCoreInterface
35

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97 memBlock.frontendBridge.icachectrl_node := l2top.inner.icachectrl_port_opt.get
98 }
99 l2top.inner.d_mmio_port := memBlock.uncache_port
100
101 // =========== IO Connection ============
102 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
103 val io = IO(new Bundle {
104 val hartId = Input(UInt(hartIdLen.W))
27import system.HasSoCParameter
28import top.{ArgParser, BusPerfMonitor, Generator}
29import utility.{ChiselDB, Constantin, DFTResetSignals, DelayN, FileRegisters, IntBuffer, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger}
30import utility.sram.SramMbistBundle
31import coupledL2.EnableCHI
32import coupledL2.tl2chi.PortIO
33import xiangshan.backend.trace.TraceCoreInterface
34

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96 memBlock.frontendBridge.icachectrl_node := l2top.inner.icachectrl_port_opt.get
97 }
98 l2top.inner.d_mmio_port := memBlock.uncache_port
99
100 // =========== IO Connection ============
101 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
102 val io = IO(new Bundle {
103 val hartId = Input(UInt(hartIdLen.W))
105 val msiInfo = Input(ValidIO(new MsiInfoBundle))
104 val msiInfo = Input(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
105 val msiAck = Output(Bool())
106 val reset_vector = Input(UInt(PAddrBits.W))
107 val cpu_halt = Output(Bool())
108 val cpu_crtical_error = Output(Bool())
109 val hartIsInReset = Output(Bool())
110 val traceCoreInterface = new TraceCoreInterface
111 val debugTopDown = new Bundle {
112 val robHeadPaddr = Valid(UInt(PAddrBits.W))
113 val l3MissMatch = Input(Bool())

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138 l2top.module.io.msiInfo.fromTile := io.msiInfo
139 core.module.io.clintTime := l2top.module.io.clintTime.toCore
140 l2top.module.io.clintTime.fromTile := io.clintTime
141 l2top.module.io.reset_vector.fromTile := io.reset_vector
142 l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt
143 io.cpu_halt := l2top.module.io.cpu_halt.toTile
144 l2top.module.io.cpu_critical_error.fromCore := core.module.io.cpu_critical_error
145 io.cpu_crtical_error := l2top.module.io.cpu_critical_error.toTile
106 val reset_vector = Input(UInt(PAddrBits.W))
107 val cpu_halt = Output(Bool())
108 val cpu_crtical_error = Output(Bool())
109 val hartIsInReset = Output(Bool())
110 val traceCoreInterface = new TraceCoreInterface
111 val debugTopDown = new Bundle {
112 val robHeadPaddr = Valid(UInt(PAddrBits.W))
113 val l3MissMatch = Input(Bool())

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138 l2top.module.io.msiInfo.fromTile := io.msiInfo
139 core.module.io.clintTime := l2top.module.io.clintTime.toCore
140 l2top.module.io.clintTime.fromTile := io.clintTime
141 l2top.module.io.reset_vector.fromTile := io.reset_vector
142 l2top.module.io.cpu_halt.fromCore := core.module.io.cpu_halt
143 io.cpu_halt := l2top.module.io.cpu_halt.toTile
144 l2top.module.io.cpu_critical_error.fromCore := core.module.io.cpu_critical_error
145 io.cpu_crtical_error := l2top.module.io.cpu_critical_error.toTile
146 l2top.module.io.msiAck.fromCore := core.module.io.msiAck
147 io.msiAck := l2top.module.io.msiAck.toTile
146
147 l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend
148 io.hartIsInReset := l2top.module.io.hartIsInReset.toTile
149 l2top.module.io.traceCoreInterface.fromCore <> core.module.io.traceCoreInterface
150 io.traceCoreInterface <> l2top.module.io.traceCoreInterface.toTile
151
152 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
153 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache

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149 l2top.module.io.hartIsInReset.resetInFrontend := core.module.io.resetInFrontend
150 io.hartIsInReset := l2top.module.io.hartIsInReset.toTile
151 l2top.module.io.traceCoreInterface.fromCore <> core.module.io.traceCoreInterface
152 io.traceCoreInterface <> l2top.module.io.traceCoreInterface.toTile
153
154 l2top.module.io.beu_errors.icache <> core.module.io.beu_errors.icache
155 l2top.module.io.beu_errors.dcache <> core.module.io.beu_errors.dcache

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