| Parameters.scala (b67f36d08f61a7fd5c69db5ec2debe7c7b6b4c9a) | Parameters.scala (627be78b11e6272c7c42f2b6b878598058ff15a9) |
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| 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 194 unchanged lines hidden (view full) --- 203 VecMemDispatchMaxNumber: Int = 16, 204 StoreBufferSize: Int = 16, 205 StoreBufferThreshold: Int = 7, 206 EnsbufferWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, | 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 194 unchanged lines hidden (view full) --- 203 VecMemDispatchMaxNumber: Int = 16, 204 StoreBufferSize: Int = 16, 205 StoreBufferThreshold: Int = 7, 206 EnsbufferWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, |
| 211 VLUopWritebackWidth: Int = 1, 212 VSUopWritebackWidth: Int = 1, |
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| 211 SplitBufferSize: Int = 8, 212 // ============================== 213 UncacheBufferSize: Int = 4, 214 EnableLoadToLoadForward: Boolean = false, 215 EnableFastForward: Boolean = true, 216 EnableLdVioCheckAfterReset: Boolean = true, 217 EnableSoftPrefetchAfterReset: Boolean = true, 218 EnableCacheErrorAfterReset: Boolean = true, --- 409 unchanged lines hidden (view full) --- 628 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 629 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 630 val StoreBufferSize = coreParams.StoreBufferSize 631 val StoreBufferThreshold = coreParams.StoreBufferThreshold 632 val EnsbufferWidth = coreParams.EnsbufferWidth 633 val VlMergeBufferSize = coreParams.VlMergeBufferSize 634 val VsMergeBufferSize = coreParams.VsMergeBufferSize 635 val UopWritebackWidth = coreParams.UopWritebackWidth | 213 SplitBufferSize: Int = 8, 214 // ============================== 215 UncacheBufferSize: Int = 4, 216 EnableLoadToLoadForward: Boolean = false, 217 EnableFastForward: Boolean = true, 218 EnableLdVioCheckAfterReset: Boolean = true, 219 EnableSoftPrefetchAfterReset: Boolean = true, 220 EnableCacheErrorAfterReset: Boolean = true, --- 409 unchanged lines hidden (view full) --- 630 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 631 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 632 val StoreBufferSize = coreParams.StoreBufferSize 633 val StoreBufferThreshold = coreParams.StoreBufferThreshold 634 val EnsbufferWidth = coreParams.EnsbufferWidth 635 val VlMergeBufferSize = coreParams.VlMergeBufferSize 636 val VsMergeBufferSize = coreParams.VsMergeBufferSize 637 val UopWritebackWidth = coreParams.UopWritebackWidth |
| 638 val VLUopWritebackWidth = coreParams.VLUopWritebackWidth 639 val VSUopWritebackWidth = coreParams.VSUopWritebackWidth |
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| 636 val SplitBufferSize = coreParams.SplitBufferSize 637 val UncacheBufferSize = coreParams.UncacheBufferSize 638 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 639 val EnableFastForward = coreParams.EnableFastForward 640 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 641 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 642 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 643 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError --- 64 unchanged lines hidden --- | 640 val SplitBufferSize = coreParams.SplitBufferSize 641 val UncacheBufferSize = coreParams.UncacheBufferSize 642 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 643 val EnableFastForward = coreParams.EnableFastForward 644 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 645 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 646 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 647 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError --- 64 unchanged lines hidden --- |