Parameters.scala (ab0200c89a96c333a11b6a9908548945f6da8cae) | Parameters.scala (15ee59e46c33fe60e4408711f9ea0a6078d50510) |
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1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 16 unchanged lines hidden (view full) --- 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ | 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 16 unchanged lines hidden (view full) --- 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ |
33import coupledL2._ |
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33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 --- 212 unchanged lines hidden (view full) --- 253 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 254 tagECC = Some("secded"), 255 dataECC = Some("secded"), 256 replacer = Some("setplru"), 257 nMissEntries = 16, 258 nProbeEntries = 8, 259 nReleaseEntries = 18 260 )), | 34import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 35 36import scala.math.min 37 38case object XSTileKey extends Field[Seq[XSCoreParameters]] 39 40case object XSCoreParamsKey extends Field[XSCoreParameters] 41 --- 212 unchanged lines hidden (view full) --- 254 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 255 tagECC = Some("secded"), 256 dataECC = Some("secded"), 257 replacer = Some("setplru"), 258 nMissEntries = 16, 259 nProbeEntries = 8, 260 nReleaseEntries = 18 261 )), |
261 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( | 262 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( |
262 name = "l2", | 263 name = "l2", |
263 level = 2, | |
264 ways = 8, 265 sets = 1024, // default 512KB L2 | 264 ways = 8, 265 sets = 1024, // default 512KB L2 |
266 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) | 266 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) |
267 )), 268 L2NBanks: Int = 1, 269 usePTWRepeater: Boolean = false, 270 softTLB: Boolean = false, // dpi-c l1tlb debug only 271 softPTW: Boolean = false, // dpi-c l2tlb debug only 272 softPTWDelay: Int = 1 273){ 274 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength --- 227 unchanged lines hidden --- | 267 )), 268 L2NBanks: Int = 1, 269 usePTWRepeater: Boolean = false, 270 softTLB: Boolean = false, // dpi-c l1tlb debug only 271 softPTW: Boolean = false, // dpi-c l2tlb debug only 272 softPTWDelay: Int = 1 273){ 274 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength --- 227 unchanged lines hidden --- |