L2Top.scala (f55cdaab615c13ad82256ecd9e8e4a84def2f8f9) L2Top.scala (1fc8b8778a8bfc722c895017ebb477b5ecdd325e)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

--- 12 unchanged lines hidden (view full) ---

21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.interrupts._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
26import freechips.rocketchip.tilelink._
27import coupledL2.{L2ParamKey, EnableCHI}
28import coupledL2.tl2tl.TL2TLCoupledL2
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

--- 12 unchanged lines hidden (view full) ---

21import org.chipsalliance.cde.config._
22import chisel3.util.{Valid, ValidIO}
23import freechips.rocketchip.diplomacy._
24import freechips.rocketchip.interrupts._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits}
26import freechips.rocketchip.tilelink._
27import coupledL2.{L2ParamKey, EnableCHI}
28import coupledL2.tl2tl.TL2TLCoupledL2
29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO}
29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue}
30import huancun.BankBitsKey
31import system.HasSoCParameter
32import top.BusPerfMonitor
33import utility._
34import xiangshan.cache.mmu.TlbRequestIO
35import xiangshan.backend.fu.PMPRespBundle
36
37class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {

--- 59 unchanged lines hidden (view full) ---

97 println(s"enableCHI: ${enableCHI}")
98 val l2cache = if (enableL2) {
99 val config = new Config((_, _, _) => {
100 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
101 hartId = p(XSCoreParamsKey).HartId,
102 FPGAPlatform = debugOpts.FPGAPlatform
103 )
104 case EnableCHI => p(EnableCHI)
30import huancun.BankBitsKey
31import system.HasSoCParameter
32import top.BusPerfMonitor
33import utility._
34import xiangshan.cache.mmu.TlbRequestIO
35import xiangshan.backend.fu.PMPRespBundle
36
37class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {

--- 59 unchanged lines hidden (view full) ---

97 println(s"enableCHI: ${enableCHI}")
98 val l2cache = if (enableL2) {
99 val config = new Config((_, _, _) => {
100 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
101 hartId = p(XSCoreParamsKey).HartId,
102 FPGAPlatform = debugOpts.FPGAPlatform
103 )
104 case EnableCHI => p(EnableCHI)
105 case CHIIssue => p(CHIIssue)
105 case BankBitsKey => log2Ceil(coreParams.L2NBanks)
106 case MaxHartIdBits => p(MaxHartIdBits)
107 case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
108 case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
109 })
110 if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
111 else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
112 } else None

--- 116 unchanged lines hidden --- 		106 case BankBitsKey => log2Ceil(coreParams.L2NBanks)
107 case MaxHartIdBits => p(MaxHartIdBits)
108 case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
109 case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
110 })
111 if (enableCHI) Some(LazyModule(new TL2CHICoupledL2()(new Config(config))))
112 else Some(LazyModule(new TL2TLCoupledL2()(new Config(config))))
113 } else None

--- 116 unchanged lines hidden ---