L2Top.scala (4a699e275a42daaf03e4f014bad0bb16d893e6ff) L2Top.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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31import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
32import huancun.BankBitsKey
33import system.HasSoCParameter
34import top.BusPerfMonitor
35import utility._
36import xiangshan.cache.mmu.TlbRequestIO
37import xiangshan.backend.fu.PMPRespBundle
38import xiangshan.backend.trace.{Itype, TraceCoreInterface}
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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31import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
32import huancun.BankBitsKey
33import system.HasSoCParameter
34import top.BusPerfMonitor
35import utility._
36import xiangshan.cache.mmu.TlbRequestIO
37import xiangshan.backend.fu.PMPRespBundle
38import xiangshan.backend.trace.{Itype, TraceCoreInterface}
39import utility.sram.SramBroadcastBundle
39
40class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
41 val ecc_error = Valid(UInt(soc.PAddrBits.W))
42}
43
44class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
45 val icache = new L1BusErrorUnitInfo
46 val dcache = new L1BusErrorUnitInfo

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103 val plic_int_node = IntIdentityNode()
104 val nmi_int_node = IntIdentityNode()
105
106 println(s"enableCHI: ${enableCHI}")
107 val l2cache = if (enableL2) {
108 val config = new Config((_, _, _) => {
109 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
110 hartId = p(XSCoreParamsKey).HartId,
40
41class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
42 val ecc_error = Valid(UInt(soc.PAddrBits.W))
43}
44
45class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
46 val icache = new L1BusErrorUnitInfo
47 val dcache = new L1BusErrorUnitInfo

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104 val plic_int_node = IntIdentityNode()
105 val nmi_int_node = IntIdentityNode()
106
107 println(s"enableCHI: ${enableCHI}")
108 val l2cache = if (enableL2) {
109 val config = new Config((_, _, _) => {
110 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
111 hartId = p(XSCoreParamsKey).HartId,
111 FPGAPlatform = debugOpts.FPGAPlatform
112 FPGAPlatform = debugOpts.FPGAPlatform,
113 hasMbist = hasMbist
112 )
113 case EnableCHI => p(EnableCHI)
114 case CHIIssue => p(CHIIssue)
115 case BankBitsKey => log2Ceil(coreParams.L2NBanks)
116 case MaxHartIdBits => p(MaxHartIdBits)
117 case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
118 case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
119 })

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212 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
213 val pfCtrlFromCore = Input(new PrefetchCtrlFromCore)
214 val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
215 val l2_pmp_resp = Flipped(new PMPRespBundle)
216 val l2_hint = ValidIO(new L2ToL1Hint())
217 val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
218 val l2_flush_en = Input(Bool())
219 val l2_flush_done = Output(Bool())
114 )
115 case EnableCHI => p(EnableCHI)
116 case CHIIssue => p(CHIIssue)
117 case BankBitsKey => log2Ceil(coreParams.L2NBanks)
118 case MaxHartIdBits => p(MaxHartIdBits)
119 case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
120 case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
121 })

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214 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
215 val pfCtrlFromCore = Input(new PrefetchCtrlFromCore)
216 val l2_tlb_req = new TlbRequestIO(nRespDups = 2)
217 val l2_pmp_resp = Flipped(new PMPRespBundle)
218 val l2_hint = ValidIO(new L2ToL1Hint())
219 val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent))
220 val l2_flush_en = Input(Bool())
221 val l2_flush_done = Output(Bool())
222 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None
223 val dft_out = if(hasMbist) Some(Output(new SramBroadcastBundle)) else None
224 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None
225 val dft_reset_out = if(hasMbist) Some(Output(new DFTResetSignals())) else None
220 // val reset_core = IO(Output(Reset()))
221 })
226 // val reset_core = IO(Output(Reset()))
227 })
228 io.dft_out.zip(io.dft).foreach({case(a, b) => a := b})
229 io.dft_reset_out.zip(io.dft_reset).foreach({case(a, b) => a := b})
222
223 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
224
225 beu.module.io.errors.icache := io.beu_errors.icache
226 beu.module.io.errors.dcache := io.beu_errors.dcache
227 resetDelayN.io.in := io.reset_vector.fromTile
228 io.reset_vector.toCore := resetDelayN.io.out
229 io.hartId.toCore := io.hartId.fromTile

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268 val hartIsInReset = RegInit(true.B)
269 hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
270 io.hartIsInReset.toTile := hartIsInReset
271
272 if (l2cache.isDefined) {
273 val l2 = l2cache.get.module
274
275 l2.io.pfCtrlFromCore := io.pfCtrlFromCore
230
231 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
232
233 beu.module.io.errors.icache := io.beu_errors.icache
234 beu.module.io.errors.dcache := io.beu_errors.dcache
235 resetDelayN.io.in := io.reset_vector.fromTile
236 io.reset_vector.toCore := resetDelayN.io.out
237 io.hartId.toCore := io.hartId.fromTile

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276 val hartIsInReset = RegInit(true.B)
277 hartIsInReset := io.hartIsInReset.resetInFrontend || reset.asBool
278 io.hartIsInReset.toTile := hartIsInReset
279
280 if (l2cache.isDefined) {
281 val l2 = l2cache.get.module
282
283 l2.io.pfCtrlFromCore := io.pfCtrlFromCore
284 l2.io.dft.zip(io.dft).foreach({case(a, b) => a := b})
285 l2.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b})
276 io.l2_hint := l2.io.l2_hint
277 l2.io.debugTopDown.robHeadPaddr := DontCare
278 l2.io.hartId := io.hartId.fromTile
279 l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
280 l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
281 io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
282 io.l2Miss := l2.io.l2Miss
283

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353 val io = IO(inner.module.io.cloneType)
354 val reset_core = IO(Output(Reset()))
355 io <> inner.module.io
356
357 if (debugOpts.ResetGen) {
358 ResetGen(ResetGenNode(Seq(
359 CellNode(reset_core),
360 ModuleNode(inner.module)
286 io.l2_hint := l2.io.l2_hint
287 l2.io.debugTopDown.robHeadPaddr := DontCare
288 l2.io.hartId := io.hartId.fromTile
289 l2.io.debugTopDown.robHeadPaddr := io.debugTopDown.robHeadPaddr
290 l2.io.debugTopDown.robTrueCommit := io.debugTopDown.robTrueCommit
291 io.debugTopDown.l2MissMatch := l2.io.debugTopDown.l2MissMatch
292 io.l2Miss := l2.io.l2Miss
293

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363 val io = IO(inner.module.io.cloneType)
364 val reset_core = IO(Output(Reset()))
365 io <> inner.module.io
366
367 if (debugOpts.ResetGen) {
368 ResetGen(ResetGenNode(Seq(
369 CellNode(reset_core),
370 ModuleNode(inner.module)
361 )), reset, sim = false)
371 )), reset, sim = false, io.dft_reset)
362 } else {
363 reset_core := DontCare
364 }
365 }
366
367 lazy val module = new Imp(this)
368}
372 } else {
373 reset_core := DontCare
374 }
375 }
376
377 lazy val module = new Imp(this)
378}