Bundle.scala (f226232f57e6b3af2007622c841418e1055b0a21) Bundle.scala (518d86588c9b2d06b514bf268da5d10fc897f3e8)
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9
10// Fetch FetchWidth x 32-bit insts from Icache
11class FetchPacket extends XSBundle {
12 val instrs = Vec(FetchWidth, UInt(32.W))
13 val mask = UInt((FetchWidth*2).W)
14 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
15 val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W))
16 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))

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31
32object ValidUndirectioned {
33 def apply[T <: Data](gen: T) = {
34 new ValidUndirectioned[T](gen)
35 }
36}
37
38class TageMeta extends XSBundle {
8
9// Fetch FetchWidth x 32-bit insts from Icache
10class FetchPacket extends XSBundle {
11 val instrs = Vec(FetchWidth, UInt(32.W))
12 val mask = UInt((FetchWidth*2).W)
13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
14 val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W))
15 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))

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30
31object ValidUndirectioned {
32 def apply[T <: Data](gen: T) = {
33 new ValidUndirectioned[T](gen)
34 }
35}
36
37class TageMeta extends XSBundle {
39 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
38// val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
40 val altDiffers = Bool()
41 val providerU = UInt(2.W)
42 val providerCtr = UInt(3.W)
39 val altDiffers = Bool()
40 val providerU = UInt(2.W)
41 val providerCtr = UInt(3.W)
43 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
42// val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
44}
45
43}
44
45// Branch prediction result from BPU Stage1 & 3
46class BranchPrediction extends XSBundle {
47 val redirect = Bool()
46class BranchPrediction extends XSBundle {
47 val redirect = Bool()
48 val jmpIdx = UInt(log2Up(PredictWidth).W)
49 val target = UInt(VAddrBits.W)
50 val saveHalfRVI = Bool()
51}
52
48
53class BranchInfo extends XSBundle {
54 val histPtr = UInt(log2Up(ExtHistoryLength).W)
55 val tageMeta = new TageMeta
49 // mask off all the instrs after the first redirect instr
50 val instrValid = Vec(FetchWidth*2, Bool())
51 // target of the first redirect instr in a fetch package
52 val target = UInt(VAddrBits.W)
53 val lateJump = Bool()
54 // save these info in brq!
55 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result
56 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))
57 // victim way when updating btb
58 // val btbVictimWay = UInt(log2Up(BtbWays).W)
59 // 2-bit saturated counter
60 val predCtr = Vec(FetchWidth*2, UInt(2.W))
61 val btbHit = Vec(FetchWidth*2, Bool())
62 // tage meta info
63 val tageMeta = Vec(FetchWidth*2, (new TageMeta))
64 // ras checkpoint, only used in Stage3
56 val rasSp = UInt(log2Up(RasSize).W)
57 val rasTopCtr = UInt(8.W)
65 val rasSp = UInt(log2Up(RasSize).W)
66 val rasTopCtr = UInt(8.W)
58
59 def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = {
60 this.histPtr := histPtr
61 this.tageMeta := tageMeta
62 this.rasSp := rasSp
63 this.rasTopCtr
64 this.asUInt
65 }
66 def size = 0.U.asTypeOf(this).getWidth
67 def fromUInt(x: UInt) = x.asTypeOf(this)
68}
69
67}
68
69// Save predecode info in icache
70class Predecode extends XSBundle {
71 val mask = UInt((FetchWidth*2).W)
70class Predecode extends XSBundle {
71 val mask = UInt((FetchWidth*2).W)
72 val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
72 val isRVC = Vec(FetchWidth*2, Bool())
73 val fuTypes = Vec(FetchWidth*2, FuType())
74 val fuOpTypes = Vec(FetchWidth*2, FuOpType())
73}
74
75
76class BranchUpdateInfo extends XSBundle {
75}
76
77
78class BranchUpdateInfo extends XSBundle {
77 // from backend
79 val fetchOffset = UInt(log2Up(FetchWidth * 4).W)
78 val pnpc = UInt(VAddrBits.W)
79 val brTarget = UInt(VAddrBits.W)
80 val pnpc = UInt(VAddrBits.W)
81 val brTarget = UInt(VAddrBits.W)
82 val hist = UInt(HistoryLength.W)
83 val btbPredCtr = UInt(2.W)
84 val btbHit = Bool()
85 val tageMeta = new TageMeta
86 val rasSp = UInt(log2Up(RasSize).W)
87 val rasTopCtr = UInt(8.W)
80 val taken = Bool()
81 val fetchIdx = UInt(log2Up(FetchWidth*2).W)
88 val taken = Bool()
89 val fetchIdx = UInt(log2Up(FetchWidth*2).W)
90 val btbType = UInt(2.W)
91 val isRVC = Bool()
92 val isBr = Bool()
82 val isMisPred = Bool()
93 val isMisPred = Bool()
83
84 // frontend -> backend -> frontend
85 val pd = new PreDecodeInfo
86 val brInfo = new BranchInfo
87}
88
89// Dequeue DecodeWidth insts from Ibuffer
90class CtrlFlow extends XSBundle {
91 val instr = UInt(32.W)
92 val pc = UInt(VAddrBits.W)
93 val exceptionVec = Vec(16, Bool())
94 val intrVec = Vec(12, Bool())

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105 val fuOpType = FuOpType()
106 val rfWen = Bool()
107 val fpWen = Bool()
108 val isXSTrap = Bool()
109 val noSpecExec = Bool() // This inst can not be speculated
110 val isBlocked = Bool() // This inst requires pipeline to be blocked
111 val isRVF = Bool()
112 val imm = UInt(XLEN.W)
94}
95
96// Dequeue DecodeWidth insts from Ibuffer
97class CtrlFlow extends XSBundle {
98 val instr = UInt(32.W)
99 val pc = UInt(VAddrBits.W)
100 val exceptionVec = Vec(16, Bool())
101 val intrVec = Vec(12, Bool())

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112 val fuOpType = FuOpType()
113 val rfWen = Bool()
114 val fpWen = Bool()
115 val isXSTrap = Bool()
116 val noSpecExec = Bool() // This inst can not be speculated
117 val isBlocked = Bool() // This inst requires pipeline to be blocked
118 val isRVF = Bool()
119 val imm = UInt(XLEN.W)
120 val dpqType = DPQType()
113}
114
115class CfCtrl extends XSBundle {
116 val cf = new CtrlFlow
117 val ctrl = new CtrlSignals
118 val brTag = new BrqPtr
119}
120

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128 )
129 }
130}
131
132// CfCtrl -> MicroOp at Rename Stage
133class MicroOp extends CfCtrl with HasRoqIdx {
134 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
135 val src1State, src2State, src3State = SrcState()
121}
122
123class CfCtrl extends XSBundle {
124 val cf = new CtrlFlow
125 val ctrl = new CtrlSignals
126 val brTag = new BrqPtr
127}
128

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136 )
137 }
138}
139
140// CfCtrl -> MicroOp at Rename Stage
141class MicroOp extends CfCtrl with HasRoqIdx {
142 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
143 val src1State, src2State, src3State = SrcState()
144 val moqIdx = UInt(MoqIdxWidth.W)
136}
137
138class Redirect extends XSBundle with HasRoqIdx {
139 val isException = Bool()
140 val isMisPred = Bool()
141 val isReplay = Bool()
142 val pc = UInt(VAddrBits.W)
143 val target = UInt(VAddrBits.W)
144 val brTag = new BrqPtr
145}
146
147class Redirect extends XSBundle with HasRoqIdx {
148 val isException = Bool()
149 val isMisPred = Bool()
150 val isReplay = Bool()
151 val pc = UInt(VAddrBits.W)
152 val target = UInt(VAddrBits.W)
153 val brTag = new BrqPtr
145 val histPtr = UInt(log2Up(ExtHistoryLength).W)
146}
147
148class Dp1ToDp2IO extends XSBundle {
154}
155
156class Dp1ToDp2IO extends XSBundle {
149 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp))
150 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp))
151 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp))
157 val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
158 val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp))
159 val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp))
152}
153
154class DebugBundle extends XSBundle{
155 val isMMIO = Bool()
156}
157
158class ExuInput extends XSBundle {
159 val uop = new MicroOp

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172class ExuIO extends XSBundle {
173 val in = Flipped(DecoupledIO(new ExuInput))
174 val redirect = Flipped(ValidIO(new Redirect))
175 val out = DecoupledIO(new ExuOutput)
176 // for csr
177 val exception = Flipped(ValidIO(new MicroOp))
178 // for Lsu
179 val dmem = new SimpleBusUC
160}
161
162class DebugBundle extends XSBundle{
163 val isMMIO = Bool()
164}
165
166class ExuInput extends XSBundle {
167 val uop = new MicroOp

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180class ExuIO extends XSBundle {
181 val in = Flipped(DecoupledIO(new ExuInput))
182 val redirect = Flipped(ValidIO(new Redirect))
183 val out = DecoupledIO(new ExuOutput)
184 // for csr
185 val exception = Flipped(ValidIO(new MicroOp))
186 // for Lsu
187 val dmem = new SimpleBusUC
180 val scommit = Input(UInt(3.W))
188 val mcommit = Input(UInt(3.W))
181}
182
183class RoqCommit extends XSBundle {
184 val uop = new MicroOp
185 val isWalk = Bool()
186}
187
188class FrontendToBackendIO extends XSBundle {
189 // to backend end
190 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
191 // from backend
192 val redirect = Flipped(ValidIO(new Redirect))
193 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
194 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
195}
189}
190
191class RoqCommit extends XSBundle {
192 val uop = new MicroOp
193 val isWalk = Bool()
194}
195
196class FrontendToBackendIO extends XSBundle {
197 // to backend end
198 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
199 // from backend
200 val redirect = Flipped(ValidIO(new Redirect))
201 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
202 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
203}