Bundle.scala (80d2974b083ab30ee12d60853063f1c370505af3) Bundle.scala (28958354979421a6ba4dca0f2897d0ca0561c159)
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9
10// Fetch FetchWidth x 32-bit insts from Icache
11class FetchPacket extends XSBundle {
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9
10// Fetch FetchWidth x 32-bit insts from Icache
11class FetchPacket extends XSBundle {
12 val instrs = Vec(FetchWidth, UInt(32.W))
13 val mask = UInt((FetchWidth*2).W)
14 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
15 val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W))
16 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))
17 // val btbVictimWay = UInt(log2Up(BtbWays).W)
18 val predCtr = Vec(FetchWidth*2, UInt(2.W))
19 val btbHit = Vec(FetchWidth*2, Bool())
20 val tageMeta = Vec(FetchWidth*2, (new TageMeta))
21 val rasSp = UInt(log2Up(RasSize).W)
22 val rasTopCtr = UInt(8.W)
12 val instrs = Vec(PredictWidth, UInt(32.W))
13 val mask = UInt(PredictWidth.W)
14 val pc = UInt(VAddrBits.W)
15 val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
16 val brInfo = Vec(PredictWidth, (new BranchInfo))
17 val pd = Vec(PredictWidth, (new PreDecodeInfo))
23}
24
18}
19
25
26class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
27 val valid = Bool()
28 val bits = gen.asInstanceOf[T]
29 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
30}
31
32object ValidUndirectioned {
33 def apply[T <: Data](gen: T) = {

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67 def fromUInt(x: UInt) = x.asTypeOf(this)
68}
69
70class Predecode extends XSBundle {
71 val mask = UInt((FetchWidth*2).W)
72 val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
73}
74
20class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
21 val valid = Bool()
22 val bits = gen.asInstanceOf[T]
23 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
24}
25
26object ValidUndirectioned {
27 def apply[T <: Data](gen: T) = {

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61 def fromUInt(x: UInt) = x.asTypeOf(this)
62}
63
64class Predecode extends XSBundle {
65 val mask = UInt((FetchWidth*2).W)
66 val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
67}
68
75
76class BranchUpdateInfo extends XSBundle {
77 // from backend
78 val pnpc = UInt(VAddrBits.W)
79 val brTarget = UInt(VAddrBits.W)
80 val taken = Bool()
81 val fetchIdx = UInt(log2Up(FetchWidth*2).W)
82 val isMisPred = Bool()
83

--- 111 unchanged lines hidden --- 		69class BranchUpdateInfo extends XSBundle {
70 // from backend
71 val pnpc = UInt(VAddrBits.W)
72 val brTarget = UInt(VAddrBits.W)
73 val taken = Bool()
74 val fetchIdx = UInt(log2Up(FetchWidth*2).W)
75 val isMisPred = Bool()
76

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