Bundle.scala (7e6acce3068fd7397d644527e57588635956aa6d) Bundle.scala (579b9f28762b9000ab852a29357f1dcc0e1636a5)
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import xiangshan.backend.brq.BrqPtr
6import xiangshan.backend.fu.fpu.Fflags
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.backend.roq.RoqPtr
9import xiangshan.mem.{LqPtr, SqPtr}
10import xiangshan.frontend.PreDecodeInfo
11import xiangshan.frontend.HasBPUParameter
12import xiangshan.frontend.HasTageParameter
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import xiangshan.backend.brq.BrqPtr
6import xiangshan.backend.fu.fpu.Fflags
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.backend.roq.RoqPtr
9import xiangshan.mem.{LqPtr, SqPtr}
10import xiangshan.frontend.PreDecodeInfo
11import xiangshan.frontend.HasBPUParameter
12import xiangshan.frontend.HasTageParameter
13import xiangshan.frontend.HasIFUConst
14import utils._
15import scala.math.max
16
17// Fetch FetchWidth x 32-bit insts from Icache
18class FetchPacket extends XSBundle {
19 val instrs = Vec(PredictWidth, UInt(32.W))
20 val mask = UInt(PredictWidth.W)
21 // val pc = UInt(VAddrBits.W)
22 val pc = Vec(PredictWidth, UInt(VAddrBits.W))
23 val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
24 val brInfo = Vec(PredictWidth, new BranchInfo)
25 val pd = Vec(PredictWidth, new PreDecodeInfo)
26 val ipf = Bool()
13import scala.math.max
14
15// Fetch FetchWidth x 32-bit insts from Icache
16class FetchPacket extends XSBundle {
17 val instrs = Vec(PredictWidth, UInt(32.W))
18 val mask = UInt(PredictWidth.W)
19 // val pc = UInt(VAddrBits.W)
20 val pc = Vec(PredictWidth, UInt(VAddrBits.W))
21 val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
22 val brInfo = Vec(PredictWidth, new BranchInfo)
23 val pd = Vec(PredictWidth, new PreDecodeInfo)
24 val ipf = Bool()
27 val acf = Bool()
28 val crossPageIPFFix = Bool()
29 val predTaken = Bool()
30}
31
32class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
33 val valid = Bool()
34 val bits = gen.cloneType.asInstanceOf[T]
35 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]

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58 val altDiffers = Bool()
59 val providerU = UInt(2.W)
60 val providerCtr = UInt(3.W)
61 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
62 val taken = Bool()
63 val scMeta = new SCMeta(EnableSC)
64}
65
25 val crossPageIPFFix = Bool()
26 val predTaken = Bool()
27}
28
29class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
30 val valid = Bool()
31 val bits = gen.cloneType.asInstanceOf[T]
32 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]

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55 val altDiffers = Bool()
56 val providerU = UInt(2.W)
57 val providerCtr = UInt(3.W)
58 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
59 val taken = Bool()
60 val scMeta = new SCMeta(EnableSC)
61}
62
66class BranchPrediction extends XSBundle with HasIFUConst {
67 // val redirect = Bool()
68 val takens = UInt(PredictWidth.W)
69 // val jmpIdx = UInt(log2Up(PredictWidth).W)
70 val brMask = UInt(PredictWidth.W)
71 val jalMask = UInt(PredictWidth.W)
72 val targets = Vec(PredictWidth, UInt(VAddrBits.W))
73
74 // marks the last 2 bytes of this fetch packet
75 // val endsAtTheEndOfFirstBank = Bool()
76 // val endsAtTheEndOfLastBank = Bool()
77
78 // half RVI could only start at the end of a bank
79 val firstBankHasHalfRVI = Bool()
80 val lastBankHasHalfRVI = Bool()
81
82 def lastHalfRVIMask = Mux(firstBankHasHalfRVI, UIntToOH((bankWidth-1).U),
83 Mux(lastBankHasHalfRVI, UIntToOH((PredictWidth-1).U),
84 0.U(PredictWidth.W)
85 )
86 )
87
88 def lastHalfRVIClearMask = ~lastHalfRVIMask
89 // is taken from half RVI
90 def lastHalfRVITaken = (takens & lastHalfRVIMask).orR
91
92 def lastHalfRVIIdx = Mux(firstBankHasHalfRVI, (bankWidth-1).U, (PredictWidth-1).U)
93 // should not be used if not lastHalfRVITaken
94 def lastHalfRVITarget = Mux(firstBankHasHalfRVI, targets(bankWidth-1), targets(PredictWidth-1))
95
96 def realTakens = takens & lastHalfRVIClearMask
97 def realBrMask = brMask & lastHalfRVIClearMask
98 def realJalMask = jalMask & lastHalfRVIClearMask
99
100 def brNotTakens = ~realTakens & realBrMask
101 def sawNotTakenBr = VecInit((0 until PredictWidth).map(i =>
102 (if (i == 0) false.B else brNotTakens(i-1,0).orR)))
103 def hasNotTakenBrs = (brNotTakens & LowerMaskFromLowest(realTakens)).orR
104 def unmaskedJmpIdx = PriorityEncoder(takens)
105 def saveHalfRVI = (firstBankHasHalfRVI && (unmaskedJmpIdx === (bankWidth-1).U || !(takens.orR))) ||
106 (lastBankHasHalfRVI && unmaskedJmpIdx === (PredictWidth-1).U)
107 // could get PredictWidth-1 when only the first bank is valid
108 def jmpIdx = PriorityEncoder(realTakens)
109 // only used when taken
110 def target = targets(jmpIdx)
111 def taken = realTakens.orR
112 def takenOnBr = taken && realBrMask(jmpIdx)
63class BranchPrediction extends XSBundle {
64 val redirect = Bool()
65 val taken = Bool()
66 val jmpIdx = UInt(log2Up(PredictWidth).W)
67 val hasNotTakenBrs = Bool()
68 val target = UInt(VAddrBits.W)
69 val saveHalfRVI = Bool()
70 val takenOnBr = Bool()
113}
114
115class BranchInfo extends XSBundle with HasBPUParameter {
116 val ubtbWriteWay = UInt(log2Up(UBtbWays).W)
117 val ubtbHits = Bool()
118 val btbWriteWay = UInt(log2Up(BtbWays).W)
119 val btbHitJal = Bool()
120 val bimCtr = UInt(2.W)

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138 this.rasSp := rasSp
139 this.rasTopCtr := rasTopCtr
140 this.asUInt
141 }
142 def size = 0.U.asTypeOf(this).getWidth
143 def fromUInt(x: UInt) = x.asTypeOf(this)
144}
145
71}
72
73class BranchInfo extends XSBundle with HasBPUParameter {
74 val ubtbWriteWay = UInt(log2Up(UBtbWays).W)
75 val ubtbHits = Bool()
76 val btbWriteWay = UInt(log2Up(BtbWays).W)
77 val btbHitJal = Bool()
78 val bimCtr = UInt(2.W)

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96 this.rasSp := rasSp
97 this.rasTopCtr := rasTopCtr
98 this.asUInt
99 }
100 def size = 0.U.asTypeOf(this).getWidth
101 def fromUInt(x: UInt) = x.asTypeOf(this)
102}
103
146class Predecode extends XSBundle with HasIFUConst {
147 val hasLastHalfRVI = Bool()
104class Predecode extends XSBundle {
105 val isFetchpcEqualFirstpc = Bool()
148 val mask = UInt((FetchWidth*2).W)
106 val mask = UInt((FetchWidth*2).W)
149 val lastHalf = UInt(nBanksInPacket.W)
150 val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
151}
152
153class BranchUpdateInfo extends XSBundle {
154 // from backend
155 val pc = UInt(VAddrBits.W)
156 val pnpc = UInt(VAddrBits.W)
157 val target = UInt(VAddrBits.W)

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171 val instr = UInt(32.W)
172 val pc = UInt(VAddrBits.W)
173 val exceptionVec = Vec(16, Bool())
174 val intrVec = Vec(12, Bool())
175 val brUpdate = new BranchUpdateInfo
176 val crossPageIPFFix = Bool()
177}
178
107 val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
108}
109
110class BranchUpdateInfo extends XSBundle {
111 // from backend
112 val pc = UInt(VAddrBits.W)
113 val pnpc = UInt(VAddrBits.W)
114 val target = UInt(VAddrBits.W)

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128 val instr = UInt(32.W)
129 val pc = UInt(VAddrBits.W)
130 val exceptionVec = Vec(16, Bool())
131 val intrVec = Vec(12, Bool())
132 val brUpdate = new BranchUpdateInfo
133 val crossPageIPFFix = Bool()
134}
135
136
137class FPUCtrlSignals extends XSBundle {
138 val tagIn = UInt(2.W)
139 val tagOut = UInt(2.W)
140}
141
179// Decode DecodeWidth insts at Decode Stage
180class CtrlSignals extends XSBundle {
181 val src1Type, src2Type, src3Type = SrcType()
182 val lsrc1, lsrc2, lsrc3 = UInt(5.W)
183 val ldest = UInt(5.W)
184 val fuType = FuType()
185 val fuOpType = FuOpType()
186 val rfWen = Bool()
187 val fpWen = Bool()
188 val isXSTrap = Bool()
189 val noSpecExec = Bool() // wait forward
190 val blockBackward = Bool() // block backward
191 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit
192 val isRVF = Bool()
193 val imm = UInt(XLEN.W)
194 val commitType = CommitType()
142// Decode DecodeWidth insts at Decode Stage
143class CtrlSignals extends XSBundle {
144 val src1Type, src2Type, src3Type = SrcType()
145 val lsrc1, lsrc2, lsrc3 = UInt(5.W)
146 val ldest = UInt(5.W)
147 val fuType = FuType()
148 val fuOpType = FuOpType()
149 val rfWen = Bool()
150 val fpWen = Bool()
151 val isXSTrap = Bool()
152 val noSpecExec = Bool() // wait forward
153 val blockBackward = Bool() // block backward
154 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit
155 val isRVF = Bool()
156 val imm = UInt(XLEN.W)
157 val commitType = CommitType()
158 val fpu = new FPUCtrlSignals
195}
196
197class CfCtrl extends XSBundle {
198 val cf = new CtrlFlow
199 val ctrl = new CtrlSignals
200 val brTag = new BrqPtr
201}
202

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295 val roqIdx = new RoqPtr
296 val hit = Bool()
297}
298
299class FrontendToBackendIO extends XSBundle {
300 // to backend end
301 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
302 // from backend
159}
160
161class CfCtrl extends XSBundle {
162 val cf = new CtrlFlow
163 val ctrl = new CtrlSignals
164 val brTag = new BrqPtr
165}
166

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259 val roqIdx = new RoqPtr
260 val hit = Bool()
261}
262
263class FrontendToBackendIO extends XSBundle {
264 // to backend end
265 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
266 // from backend
303 val redirect = Flipped(ValidIO(UInt(VAddrBits.W)))
267 val redirect = Flipped(ValidIO(new Redirect))
304 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
305 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
306}
307
308class TlbCsrBundle extends XSBundle {
309 val satp = new Bundle {
310 val mode = UInt(4.W) // TODO: may change number to parameter
311 val asid = UInt(16.W)

--- 27 unchanged lines hidden --- 		268 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
269 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
270}
271
272class TlbCsrBundle extends XSBundle {
273 val satp = new Bundle {
274 val mode = UInt(4.W) // TODO: may change number to parameter
275 val asid = UInt(16.W)

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