Trigger.scala (8241cb85f7d34397435cf2810442754e2a0f477d) Trigger.scala (45f43e6e5f88874a7573ff096d1e5c2855bd16c7)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mu lan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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17package utils
18
19import chisel3._
20import chisel3.util._
21import xiangshan.MatchTriggerIO
22import org.chipsalliance.cde.config.Parameters
23
24
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mu lan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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17package utils
18
19import chisel3._
20import chisel3.util._
21import xiangshan.MatchTriggerIO
22import org.chipsalliance.cde.config.Parameters
23
24
25object TriggerCmp {
26 def apply(actual: UInt, tdata: UInt, matchType: UInt, enable: Bool) = {
27 val equal = actual === tdata
28 val greater = actual >= tdata
29 val less = actual <= tdata
30 val res = MuxLookup(matchType, false.B)(
31 Array(0.U -> equal,
32 2.U -> greater,
33 3.U -> less))
34 res && enable
35 }
36}
37
25object TriggerCmpConsecutive {
26 def apply(actual: Vec[UInt], tdata: UInt, matchType: UInt, enable: Bool, VAddrBits: Int) : Vec[Bool] = {
27 // opt: only compare two possible high bits: orig and orig+1
28 val len1 = actual.length
29 val highPos = log2Up(len1)
30 val lowPC = Wire(Vec(len1, UInt(highPos.W)))
31 lowPC.zipWithIndex.map{case (h, i) => h := actual(i)(highPos - 1, 0)}
32 val highPC = actual(0)(VAddrBits - 1, highPos)

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60 // greater: 1. highPC > highTdata; 2. highPC == highTdata && lowPC >= lowTdata
61 overallGreater.zipWithIndex.map{case (o, i) => o := highPCGreater || ((!carry(i) || lowPCGreater(i)) && highPCEqual)}
62
63 // less: 1. highPC < highTdata; 2. highPC == highTdata && lowPC <= lowTdata
64 overallLess.zipWithIndex.map{case (o, i) => o := highPCLess || ((!carry(i) && lowPCLess(i)) && highPCEqual)}
65
66 val ret = Wire(Vec(len1, Bool()))
67
38object TriggerCmpConsecutive {
39 def apply(actual: Vec[UInt], tdata: UInt, matchType: UInt, enable: Bool, VAddrBits: Int) : Vec[Bool] = {
40 // opt: only compare two possible high bits: orig and orig+1
41 val len1 = actual.length
42 val highPos = log2Up(len1)
43 val lowPC = Wire(Vec(len1, UInt(highPos.W)))
44 lowPC.zipWithIndex.map{case (h, i) => h := actual(i)(highPos - 1, 0)}
45 val highPC = actual(0)(VAddrBits - 1, highPos)

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73 // greater: 1. highPC > highTdata; 2. highPC == highTdata && lowPC >= lowTdata
74 overallGreater.zipWithIndex.map{case (o, i) => o := highPCGreater || ((!carry(i) || lowPCGreater(i)) && highPCEqual)}
75
76 // less: 1. highPC < highTdata; 2. highPC == highTdata && lowPC <= lowTdata
77 overallLess.zipWithIndex.map{case (o, i) => o := highPCLess || ((!carry(i) && lowPCLess(i)) && highPCEqual)}
78
79 val ret = Wire(Vec(len1, Bool()))
80
68 ret.zipWithIndex.map{case (r, i) => r := MuxLookup(matchType, false.B,
81 ret.zipWithIndex.map{case (r, i) => r := MuxLookup(matchType, false.B)(
69 Array(0.U -> overallEqual(i),
70 2.U -> overallGreater(i),
71 3.U -> overallLess(i))) && enable}
72 ret
73 }
74}
75
76object ChainCheck {
77 def TimingCheck(prevTiming: Bool, thisTiming: Bool, chain: Bool) = !((prevTiming ^ thisTiming) && chain)
78 def HitCheck(prevHit: Bool, chain: Bool) = prevHit || !chain
79}
80
81object PrintTriggerInfo {
82 def apply(enable: Bool, trigger: MatchTriggerIO)(implicit p: Parameters) = {
83 XSDebug(enable, p"Debug Mode: Match Type is ${trigger.matchType}; select is ${trigger.select};" +
84 p"timing is ${trigger.timing}; action is ${trigger.action}; chain is ${trigger.chain};" +
85 p"tdata2 is ${Hexadecimal(trigger.tdata2)}")
86 }
87}
82 Array(0.U -> overallEqual(i),
83 2.U -> overallGreater(i),
84 3.U -> overallLess(i))) && enable}
85 ret
86 }
87}
88
89object ChainCheck {
90 def TimingCheck(prevTiming: Bool, thisTiming: Bool, chain: Bool) = !((prevTiming ^ thisTiming) && chain)
91 def HitCheck(prevHit: Bool, chain: Bool) = prevHit || !chain
92}
93
94object PrintTriggerInfo {
95 def apply(enable: Bool, trigger: MatchTriggerIO)(implicit p: Parameters) = {
96 XSDebug(enable, p"Debug Mode: Match Type is ${trigger.matchType}; select is ${trigger.select};" +
97 p"timing is ${trigger.timing}; action is ${trigger.action}; chain is ${trigger.chain};" +
98 p"tdata2 is ${Hexadecimal(trigger.tdata2)}")
99 }
100}