XSNoCTop.scala (e8b2ab2c3f0cc3a428522e4ecd069333e3b0b3e8) XSNoCTop.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import chisel3.experimental.dataview._
21import xiangshan._
22import utils._
23import utility._
24import utility.sram.SramMbistBundle
25import system._
26import device._
27import org.chipsalliance.cde.config._
28import freechips.rocketchip.amba.axi4._

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63
64 // xstile
65 val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
66 case XSCoreParamsKey => tiles.head
67 case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
68 })))
69
70 // imsic bus top
22import xiangshan._
23import utils._
24import utility._
25import utility.sram.SramMbistBundle
26import system._
27import device._
28import org.chipsalliance.cde.config._
29import freechips.rocketchip.amba.axi4._

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64
65 // xstile
66 val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
67 case XSCoreParamsKey => tiles.head
68 case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
69 })))
70
71 // imsic bus top
71 val u_imsic_bus_top = LazyModule(new imsic_bus_top(
72 useTL = soc.IMSICUseTL,
73 baseAddress = (0x3A800000, 0x3B000000)
74 ))
72 val u_imsic_bus_top = LazyModule(new imsic_bus_top)
75
76 // interrupts
77 val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
78 val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
79 val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
80 val nmiIntNode = IntSourceNode(IntSourcePortSimple(1, 1, (new NonmaskableInterruptIO).elements.size))
81 val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
82 core_with_l2.clintIntNode := clintIntNode

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173 val ilastsize = UInt((TraceTraceGroupNum * TraceIlastsizeWidth).W)
174 })
175 }
176 val dft = Option.when(hasMbist)(Input(new SramMbistBundle))
177 val dft_reset = Option.when(hasMbist)(Input(new DFTResetSignals()))
178 val sramCtl = Option.when(hasSramCtl)(Input(UInt(64.W)))
179 val lp = Option.when(EnablePowerDown) (new LowPowerIO)
180 })
73
74 // interrupts
75 val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
76 val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
77 val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
78 val nmiIntNode = IntSourceNode(IntSourcePortSimple(1, 1, (new NonmaskableInterruptIO).elements.size))
79 val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
80 core_with_l2.clintIntNode := clintIntNode

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171 val ilastsize = UInt((TraceTraceGroupNum * TraceIlastsizeWidth).W)
172 })
173 }
174 val dft = Option.when(hasMbist)(Input(new SramMbistBundle))
175 val dft_reset = Option.when(hasMbist)(Input(new DFTResetSignals()))
176 val sramCtl = Option.when(hasSramCtl)(Input(UInt(64.W)))
177 val lp = Option.when(EnablePowerDown) (new LowPowerIO)
178 })
181 // imsic axi4lite io
182 val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
179 // imsic axi4 io
180 val imsic_axi4 = wrapper.u_imsic_bus_top.axi4.map(x => IO(Flipped(new VerilogAXI4Record(x.elts.head.params.copy(addrBits = 32)))))
183 // imsic tl io
184 val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
185 val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
181 // imsic tl io
182 val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
183 val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
184 // imsic bare io
185 val imsic = wrapper.u_imsic_bus_top.module.msi.map(x => IO(chiselTypeOf(x)))
186
187 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen(2, io.dft_reset) })
188 val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen(2, io.dft_reset) }
189 wrapper.core_with_l2.module.io.sramTest.mbist.zip(io.dft).foreach { case (a, b) => a := b }
190 wrapper.core_with_l2.module.io.sramTest.mbistReset.zip(io.dft_reset).foreach { case (a, b) => a := b }
191 wrapper.core_with_l2.module.io.sramTest.sramCtl.zip(io.sramCtl).foreach { case (a, b) => a := b }
192 // device clock and reset
193 wrapper.u_imsic_bus_top.module.clock := soc_clock
194 wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
195
186
187 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen(2, io.dft_reset) })
188 val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen(2, io.dft_reset) }
189 wrapper.core_with_l2.module.io.sramTest.mbist.zip(io.dft).foreach { case (a, b) => a := b }
190 wrapper.core_with_l2.module.io.sramTest.mbistReset.zip(io.dft_reset).foreach { case (a, b) => a := b }
191 wrapper.core_with_l2.module.io.sramTest.sramCtl.zip(io.sramCtl).foreach { case (a, b) => a := b }
192 // device clock and reset
193 wrapper.u_imsic_bus_top.module.clock := soc_clock
194 wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
195
196 // imsic axi4lite io connection
197 wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
198
196 // imsic axi4 io connection
197 imsic_axi4.foreach(_.viewAs[AXI4Bundle] <> wrapper.u_imsic_bus_top.axi4.get.elements.head._2)
199 // imsic tl io connection
200 wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
201 wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
198 // imsic tl io connection
199 wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
200 wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
201 // imsic bare io connection
202 wrapper.u_imsic_bus_top.module.msi.foreach(_ <> imsic.get)
202
203 // input
204 dontTouch(io)
205
206 /*
207 SoC control the sequence of power on/off with isolation/reset/clock
208 */
209 val soc_rst_n = io.lp.map(_.i_cpu_sw_rst_n).getOrElse(true.B)

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330 }
331
332 // Seperate DebugModule TL Async Queue Sink
333 if (SeperateTLBus && EnableSeperateTLAsync) {
334 tlAsyncSinkOpt.get.module.clock := soc_clock
335 tlAsyncSinkOpt.get.module.reset := soc_reset_sync
336 }
337
203
204 // input
205 dontTouch(io)
206
207 /*
208 SoC control the sequence of power on/off with isolation/reset/clock
209 */
210 val soc_rst_n = io.lp.map(_.i_cpu_sw_rst_n).getOrElse(true.B)

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331 }
332
333 // Seperate DebugModule TL Async Queue Sink
334 if (SeperateTLBus && EnableSeperateTLAsync) {
335 tlAsyncSinkOpt.get.module.clock := soc_clock
336 tlAsyncSinkOpt.get.module.reset := soc_reset_sync
337 }
338
338 core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
339 core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
339 core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.msiio.vld_req
340 core_with_l2.module.io.msiInfo.bits := wrapper.u_imsic_bus_top.module.msiio.data
341 wrapper.u_imsic_bus_top.module.msiio.vld_ack := core_with_l2.module.io.msiAck
340 // tie off core soft reset
341 core_rst_node.out.head._1 := false.B.asAsyncReset
342
343 core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
344 core_with_l2.module.io.l3Miss := false.B
345 }
346
347 lazy val module = new XSNoCTopImp(this)

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370 exposeIO(l_soc.nmi, "nmi")
371 soc.clock := clock
372 soc.reset := reset.asAsyncReset
373 exposeIO(soc.soc_clock, "soc_clock")
374 exposeIO(soc.soc_reset, "soc_reset")
375 exposeIO(soc.io, "io")
376 exposeOptionIO(soc.noc_clock, "noc_clock")
377 exposeOptionIO(soc.noc_reset, "noc_reset")
342 // tie off core soft reset
343 core_rst_node.out.head._1 := false.B.asAsyncReset
344
345 core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
346 core_with_l2.module.io.l3Miss := false.B
347 }
348
349 lazy val module = new XSNoCTopImp(this)

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372 exposeIO(l_soc.nmi, "nmi")
373 soc.clock := clock
374 soc.reset := reset.asAsyncReset
375 exposeIO(soc.soc_clock, "soc_clock")
376 exposeIO(soc.soc_reset, "soc_reset")
377 exposeIO(soc.io, "io")
378 exposeOptionIO(soc.noc_clock, "noc_clock")
379 exposeOptionIO(soc.noc_reset, "noc_reset")
378 exposeOptionIO(soc.imsic_axi4lite, "imsic_axi4lite")
380 exposeOptionIO(soc.imsic_axi4, "imsic_axi4")
381 exposeOptionIO(soc.imsic_m_tl, "imsic_m_tl")
382 exposeOptionIO(soc.imsic_s_tl, "imsic_s_tl")
383 exposeOptionIO(soc.imsic, "imsic")
379
380 // TODO:
381 // XSDiffTop is only part of DUT, we can not instantiate difftest here.
382 // Temporarily we collect Performance counters for each DiffTop, need control signals passed from Difftest
383 val timer = IO(Input(UInt(64.W)))
384 val logEnable = IO(Input(Bool()))
385 val clean = IO(Input(Bool()))
386 val dump = IO(Input(Bool()))

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385 // TODO:
386 // XSDiffTop is only part of DUT, we can not instantiate difftest here.
387 // Temporarily we collect Performance counters for each DiffTop, need control signals passed from Difftest
388 val timer = IO(Input(UInt(64.W)))
389 val logEnable = IO(Input(Bool()))
390 val clean = IO(Input(Bool()))
391 val dump = IO(Input(Bool()))

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