XSNoCTop.scala (4a699e275a42daaf03e4f014bad0bb16d893e6ff) XSNoCTop.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.devices.debug.DebugModuleKey
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.interrupts._
31import freechips.rocketchip.tilelink._
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.devices.debug.DebugModuleKey
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.interrupts._
31import freechips.rocketchip.tilelink._
32import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import coupledL2.tl2chi.{CHIAsyncBridgeSink, PortIO}
33import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.tile.MaxHartIdBits
34import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
35import chisel3.experimental.{annotate, ChiselAnnotation}
34import freechips.rocketchip.util.{AsyncQueueParams, AsyncQueueSource}
35import chisel3.experimental.{ChiselAnnotation, annotate}
36import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
36import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
37import utility.sram.SramBroadcastBundle
37
38import difftest.common.DifftestWiring
39import difftest.util.Profile
40
41class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
42{
43 override lazy val desiredName: String = "XSTop"
44

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140 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
141
142 val clock = IO(Input(Clock()))
143 val reset = IO(Input(AsyncReset()))
144 val noc_clock = EnableCHIAsyncBridge.map(_ => IO(Input(Clock())))
145 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
146 val soc_clock = IO(Input(Clock()))
147 val soc_reset = IO(Input(AsyncReset()))
38
39import difftest.common.DifftestWiring
40import difftest.util.Profile
41
42class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
43{
44 override lazy val desiredName: String = "XSTop"
45

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141 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
142
143 val clock = IO(Input(Clock()))
144 val reset = IO(Input(AsyncReset()))
145 val noc_clock = EnableCHIAsyncBridge.map(_ => IO(Input(Clock())))
146 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
147 val soc_clock = IO(Input(Clock()))
148 val soc_reset = IO(Input(AsyncReset()))
149 private val hasMbist = tiles.head.hasMbist
148 val io = IO(new Bundle {
149 val hartId = Input(UInt(p(MaxHartIdBits).W))
150 val riscv_halt = Output(Bool())
151 val riscv_critical_error = Output(Bool())
152 val hartResetReq = Input(Bool())
153 val hartIsInReset = Output(Bool())
154 val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
155 val chi = new PortIO

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165 val tval = UInt(TraceTvalWidth.W)
166 val priv = UInt(TracePrivWidth.W)
167 val iaddr = UInt((TraceTraceGroupNum * TraceIaddrWidth).W)
168 val itype = UInt((TraceTraceGroupNum * TraceItypeWidth).W)
169 val iretire = UInt((TraceTraceGroupNum * TraceIretireWidthCompressed).W)
170 val ilastsize = UInt((TraceTraceGroupNum * TraceIlastsizeWidth).W)
171 })
172 }
150 val io = IO(new Bundle {
151 val hartId = Input(UInt(p(MaxHartIdBits).W))
152 val riscv_halt = Output(Bool())
153 val riscv_critical_error = Output(Bool())
154 val hartResetReq = Input(Bool())
155 val hartIsInReset = Output(Bool())
156 val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
157 val chi = new PortIO

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167 val tval = UInt(TraceTvalWidth.W)
168 val priv = UInt(TracePrivWidth.W)
169 val iaddr = UInt((TraceTraceGroupNum * TraceIaddrWidth).W)
170 val itype = UInt((TraceTraceGroupNum * TraceItypeWidth).W)
171 val iretire = UInt((TraceTraceGroupNum * TraceIretireWidthCompressed).W)
172 val ilastsize = UInt((TraceTraceGroupNum * TraceIlastsizeWidth).W)
173 })
174 }
175 val dft = if(hasMbist) Some(Input(new SramBroadcastBundle)) else None
176 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals())) else None
173 })
174 // imsic axi4lite io
175 val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
176 // imsic tl io
177 val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
178 val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
179
177 })
178 // imsic axi4lite io
179 val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
180 // imsic tl io
181 val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
182 val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
183
180 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen() })
181 val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
182
184 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen(2, io.dft_reset) })
185 val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen(2, io.dft_reset) }
186 wrapper.core_with_l2.module.io.dft.zip(io.dft).foreach({case(a, b) => a := b})
187 wrapper.core_with_l2.module.io.dft_reset.zip(io.dft_reset).foreach({case(a, b) => a := b})
183 // device clock and reset
184 wrapper.u_imsic_bus_top.module.clock := soc_clock
185 wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
186
187 // imsic axi4lite io connection
188 wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
189
190 // imsic tl io connection

--- 173 unchanged lines hidden --- 		188 // device clock and reset
189 wrapper.u_imsic_bus_top.module.clock := soc_clock
190 wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
191
192 // imsic axi4lite io connection
193 wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
194
195 // imsic tl io connection

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