Top.scala (9672f0b7124446b0dbe8f0a1e831208f22e01305) Top.scala (a5b77de44ecd30ff2bbdebcfd07ca41d86e70db9)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import utility._
25import system._
26import device._
27import chisel3.stage.ChiselGeneratorAnnotation
28import org.chipsalliance.cde.config._
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.tilelink._
31import freechips.rocketchip.jtag.JTAGIO
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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24import utility._
25import system._
26import device._
27import chisel3.stage.ChiselGeneratorAnnotation
28import org.chipsalliance.cde.config._
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.tilelink._
31import freechips.rocketchip.jtag.JTAGIO
32import chisel3.experimental.{annotate, ChiselAnnotation}
33import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
32
33abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
34 with BindingScope
35{
36 val misc = LazyModule(new SoCMisc())
37 lazy val dts = DTS(bindingTree)
38 lazy val json = JSON(bindingTree)
39}

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133 println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
134 core.core_l3_tpmeta_sink_port.get := broadcast.node
135 }
136 })
137 case None =>
138 }
139
140 class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
34
35abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
36 with BindingScope
37{
38 val misc = LazyModule(new SoCMisc())
39 lazy val dts = DTS(bindingTree)
40 lazy val json = JSON(bindingTree)
41}

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135 println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
136 core.core_l3_tpmeta_sink_port.get := broadcast.node
137 }
138 })
139 case None =>
140 }
141
142 class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
143 soc.XSTopPrefix.foreach { prefix =>
144 val mod = this.toNamed
145 annotate(new ChiselAnnotation {
146 def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
147 })
148 }
149
141 FileRegisters.add("dts", dts)
142 FileRegisters.add("graphml", graphML)
143 FileRegisters.add("json", json)
144 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
145
146 val dma = IO(Flipped(misc.dma.cloneType))
147 val peripheral = IO(misc.peripheral.cloneType)
148 val memory = IO(misc.memory.cloneType)

--- 122 unchanged lines hidden --- 		150 FileRegisters.add("dts", dts)
151 FileRegisters.add("graphml", graphML)
152 FileRegisters.add("json", json)
153 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
154
155 val dma = IO(Flipped(misc.dma.cloneType))
156 val peripheral = IO(misc.peripheral.cloneType)
157 val memory = IO(misc.memory.cloneType)

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