Top.scala (4a699e275a42daaf03e4f014bad0bb16d893e6ff) Top.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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323 io.traceCoreInterface(i).toEncoder.priv := traceInterface.toEncoder.priv
324 io.traceCoreInterface(i).toEncoder.cause := traceInterface.toEncoder.trap.cause
325 io.traceCoreInterface(i).toEncoder.tval := traceInterface.toEncoder.trap.tval
326 io.traceCoreInterface(i).toEncoder.iaddr := VecInit(traceInterface.toEncoder.groups.map(_.bits.iaddr)).asUInt
327 io.traceCoreInterface(i).toEncoder.itype := VecInit(traceInterface.toEncoder.groups.map(_.bits.itype)).asUInt
328 io.traceCoreInterface(i).toEncoder.iretire := VecInit(traceInterface.toEncoder.groups.map(_.bits.iretire)).asUInt
329 io.traceCoreInterface(i).toEncoder.ilastsize := VecInit(traceInterface.toEncoder.groups.map(_.bits.ilastsize)).asUInt
330
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

--- 314 unchanged lines hidden (view full) ---

323 io.traceCoreInterface(i).toEncoder.priv := traceInterface.toEncoder.priv
324 io.traceCoreInterface(i).toEncoder.cause := traceInterface.toEncoder.trap.cause
325 io.traceCoreInterface(i).toEncoder.tval := traceInterface.toEncoder.trap.tval
326 io.traceCoreInterface(i).toEncoder.iaddr := VecInit(traceInterface.toEncoder.groups.map(_.bits.iaddr)).asUInt
327 io.traceCoreInterface(i).toEncoder.itype := VecInit(traceInterface.toEncoder.groups.map(_.bits.itype)).asUInt
328 io.traceCoreInterface(i).toEncoder.iretire := VecInit(traceInterface.toEncoder.groups.map(_.bits.iretire)).asUInt
329 io.traceCoreInterface(i).toEncoder.ilastsize := VecInit(traceInterface.toEncoder.groups.map(_.bits.ilastsize)).asUInt
330
331 core.module.io.dft.foreach(_ := DontCare)
332 core.module.io.dft_reset.foreach(_ := DontCare)
331 core.module.io.reset_vector := io.riscv_rst_vec(i)
332 }
333
334 withClockAndReset(io.clock, io.reset) {
335 Option.when(enableCHI)(true.B).foreach { _ =>
336 for ((core, i) <- core_with_l2.zipWithIndex) {
337 val mmioLogger = CHILogger(s"L2[${i}]_MMIO", true)
338 val llcLogger = CHILogger(s"L2[${i}]_LLC", true)

--- 133 unchanged lines hidden --- 		333 core.module.io.reset_vector := io.riscv_rst_vec(i)
334 }
335
336 withClockAndReset(io.clock, io.reset) {
337 Option.when(enableCHI)(true.B).foreach { _ =>
338 for ((core, i) <- core_with_l2.zipWithIndex) {
339 val mmioLogger = CHILogger(s"L2[${i}]_MMIO", true)
340 val llcLogger = CHILogger(s"L2[${i}]_LLC", true)

--- 133 unchanged lines hidden ---