Top.scala (2316cea82d361ad8b181fc0912feb662dc1dc4a8) Top.scala (2993c5ecece73b73073301e23435ca1b763d0b5f)
1/***************************************************************************************
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9* http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
21import difftest.DifftestModule
22import xiangshan._
23import utils._
24import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
25import coupledL2.EnableCHI
26import utility._
27import system._
28import device._

--- 140 unchanged lines hidden (view full) ---

169 })
170 }
171
172 FileRegisters.add("dts", dts)
173 FileRegisters.add("graphml", graphML)
174 FileRegisters.add("json", json)
175 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
176
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
28import utility._
29import system._
30import device._

--- 140 unchanged lines hidden (view full) ---

171 })
172 }
173
174 FileRegisters.add("dts", dts)
175 FileRegisters.add("graphml", graphML)
176 FileRegisters.add("json", json)
177 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
178
177 val dma = socMisc.map(m => IO(Flipped(m.dma.cloneType)))
178 val peripheral = socMisc.map(m => IO(m.peripheral.cloneType))
179 val memory = IO(misc.memory.cloneType)
179 val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
180 val peripheral = socMisc.map(m => IO(new VerilogAXI4Record(m.peripheral.elts.head.params)))
181 val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
180
181 socMisc match {
182 case Some(m) =>
182
183 socMisc match {
184 case Some(m) =>
183 m.dma <> dma.get
184 peripheral.get <> m.peripheral
185 m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
186 peripheral.get.viewAs[AXI4Bundle] <> m.peripheral.elements.head._2
185 dontTouch(dma.get)
186 dontTouch(peripheral.get)
187 case None =>
188 }
187 dontTouch(dma.get)
188 dontTouch(peripheral.get)
189 case None =>
190 }
189
190 memory <> misc.memory
191
191
192 memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
193
192 val io = IO(new Bundle {
193 val clock = Input(Bool())
194 val reset = Input(AsyncReset())
195 val sram_config = Input(UInt(16.W))
196 val extIntrs = Input(UInt(NrExtIntr.W))
197 val pll0_lock = Input(Bool())
198 val pll0_ctrl = Output(Vec(6, UInt(32.W)))
199 val systemjtag = new Bundle {

--- 125 unchanged lines hidden --- 		194 val io = IO(new Bundle {
195 val clock = Input(Bool())
196 val reset = Input(AsyncReset())
197 val sram_config = Input(UInt(16.W))
198 val extIntrs = Input(UInt(NrExtIntr.W))
199 val pll0_lock = Input(Bool())
200 val pll0_ctrl = Output(Vec(6, UInt(32.W)))
201 val systemjtag = new Bundle {

--- 125 unchanged lines hidden ---