Configs.scala (e524aeedab50586b2dbc86a2180380085c43a4cd) Configs.scala (53bd4e1cb2bbe049a6887a8f3c75c296803c14b0)
1/***************************************************************************************
2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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278})
279
280case class L2CacheConfig
281(
282 size: String,
283 ways: Int = 8,
284 inclusive: Boolean = true,
285 banks: Int = 1,
1/***************************************************************************************
2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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278})
279
280case class L2CacheConfig
281(
282 size: String,
283 ways: Int = 8,
284 inclusive: Boolean = true,
285 banks: Int = 1,
286 tp: Boolean = true
286 tp: Boolean = true,
287 enableFlush: Boolean = false
287) extends Config((site, here, up) => {
288 case XSTileKey =>
289 require(inclusive, "L2 must be inclusive")
290 val nKB = size.toUpperCase() match {
291 case s"${k}KB" => k.trim().toInt
292 case s"${m}MB" => (m.trim().toDouble * 1024).toInt
293 }
294 val upParams = up(XSTileKey)

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312 dataECC = Some("secded"),
313 enableTagECC = true,
314 enableDataECC = true,
315 dataCheck = Some("oddparity"),
316 enablePoison = true,
317 prefetch = Seq(BOPParameters()) ++
318 (if (tp) Seq(TPParameters()) else Nil) ++
319 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil),
288) extends Config((site, here, up) => {
289 case XSTileKey =>
290 require(inclusive, "L2 must be inclusive")
291 val nKB = size.toUpperCase() match {
292 case s"${k}KB" => k.trim().toInt
293 case s"${m}MB" => (m.trim().toDouble * 1024).toInt
294 }
295 val upParams = up(XSTileKey)

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313 dataECC = Some("secded"),
314 enableTagECC = true,
315 enableDataECC = true,
316 dataCheck = Some("oddparity"),
317 enablePoison = true,
318 prefetch = Seq(BOPParameters()) ++
319 (if (tp) Seq(TPParameters()) else Nil) ++
320 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil),
321 enableL2Flush = enableFlush,
320 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug,
321 enableRollingDB = site(DebugOptionsKey).EnableRollingDB,
322 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB,
323 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform,
324 hasMbist = p.hasMbist,
325 hasSramCtl = p.hasSramCtl,
326 )),
327 L2NBanks = banks

--- 237 unchanged lines hidden --- 		322 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug,
323 enableRollingDB = site(DebugOptionsKey).EnableRollingDB,
324 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB,
325 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform,
326 hasMbist = p.hasMbist,
327 hasSramCtl = p.hasSramCtl,
328 )),
329 L2NBanks = banks

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