Configs.scala (e4f69d78f24895ac36a5a6c704cec53e4af72485) Configs.scala (15ee59e46c33fe60e4408711f9ea0a6078d50510)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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28import freechips.rocketchip.devices.debug._
29import freechips.rocketchip.tile.MaxHartIdBits
30import xiangshan.backend.dispatch.DispatchParameters
31import xiangshan.backend.exu.ExuParameters
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
34import device.{EnableJtag, XSDebugModuleParams}
35import huancun._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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28import freechips.rocketchip.devices.debug._
29import freechips.rocketchip.tile.MaxHartIdBits
30import xiangshan.backend.dispatch.DispatchParameters
31import xiangshan.backend.exu.ExuParameters
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
34import device.{EnableJtag, XSDebugModuleParams}
35import huancun._
36import coupledL2._
36
37class BaseConfig(n: Int) extends Config((site, here, up) => {
38 case XLen => 64
39 case DebugOptionsKey => DebugOptions()
40 case SoCParamsKey => SoCParameters()
41 case PMParameKey => PMParameters()
42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))

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175 l2tlbParameters = L2TLBParameters(
176 l1Size = 4,
177 l2nSets = 4,
178 l2nWays = 4,
179 l3nSets = 4,
180 l3nWays = 8,
181 spSize = 2,
182 ),
37
38class BaseConfig(n: Int) extends Config((site, here, up) => {
39 case XLen => 64
40 case DebugOptionsKey => DebugOptions()
41 case SoCParamsKey => SoCParameters()
42 case PMParameKey => PMParameters()
43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))

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176 l2tlbParameters = L2TLBParameters(
177 l1Size = 4,
178 l2nSets = 4,
179 l2nWays = 4,
180 l3nSets = 4,
181 l3nWays = 8,
182 spSize = 2,
183 ),
183 L2CacheParamsOpt = None, // remove L2 Cache
184 L2CacheParamsOpt = Some(L2Param(
185 name = "L2",
186 ways = 8,
187 sets = 128,
188 echoField = Seq(huancun.DirtyField()),
189 prefetch = None
190 )),
191 L2NBanks = 2,
184 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher
185 )
186 )
187 case SoCParamsKey =>
188 val tiles = site(XSTileKey)
189 up(SoCParamsKey).copy(
190 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
191 sets = 1024,
192 inclusive = false,
192 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher
193 )
194 )
195 case SoCParamsKey =>
196 val tiles = site(XSTileKey)
197 up(SoCParamsKey).copy(
198 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
199 sets = 1024,
200 inclusive = false,
193 clientCaches = tiles.map{ p =>
194 CacheParameters(
195 "dcache",
196 sets = 2 * p.dcacheParametersOpt.get.nSets,
197 ways = p.dcacheParametersOpt.get.nWays + 2,
198 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets),
199 aliasBitsOpt = None
200 )
201 clientCaches = tiles.map{ core =>
202 val clientDirBytes = tiles.map{ t =>
203 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0)
204 }.sum
205 val l2params = core.L2CacheParamsOpt.get.toCacheParams
206 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64)
201 },
202 simulation = !site(DebugOptionsKey).FPGAPlatform
203 )),
204 L3NBanks = 1
205 )
206 })
207)
208

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243 inclusive: Boolean = true,
244 banks: Int = 1,
245 alwaysReleaseData: Boolean = false
246) extends Config((site, here, up) => {
247 case XSTileKey =>
248 val upParams = up(XSTileKey)
249 val l2sets = n * 1024 / banks / ways / 64
250 upParams.map(p => p.copy(
207 },
208 simulation = !site(DebugOptionsKey).FPGAPlatform
209 )),
210 L3NBanks = 1
211 )
212 })
213)
214

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249 inclusive: Boolean = true,
250 banks: Int = 1,
251 alwaysReleaseData: Boolean = false
252) extends Config((site, here, up) => {
253 case XSTileKey =>
254 val upParams = up(XSTileKey)
255 val l2sets = n * 1024 / banks / ways / 64
256 upParams.map(p => p.copy(
251 L2CacheParamsOpt = Some(HCCacheParameters(
257 L2CacheParamsOpt = Some(L2Param(
252 name = "L2",
258 name = "L2",
253 level = 2,
254 ways = ways,
255 sets = l2sets,
259 ways = ways,
260 sets = l2sets,
256 inclusive = inclusive,
257 alwaysReleaseData = alwaysReleaseData,
258 clientCaches = Seq(CacheParameters(
261 clientCaches = Seq(L1Param(
259 "dcache",
260 sets = 2 * p.dcacheParametersOpt.get.nSets / banks,
261 ways = p.dcacheParametersOpt.get.nWays + 2,
262 "dcache",
263 sets = 2 * p.dcacheParametersOpt.get.nSets / banks,
264 ways = p.dcacheParametersOpt.get.nWays + 2,
262 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks),
263 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
264 )),
265 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
266 )),
265 reqField = Seq(PreferCacheField()),
266 echoField = Seq(DirtyField()),
267 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()),
268 enablePerf = true,
269 sramDepthDiv = 2,
270 tagECC = Some("secded"),
271 dataECC = Some("secded"),
272 simulation = !site(DebugOptionsKey).FPGAPlatform
267 echoField = Seq(huancun.DirtyField()),
268 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams())
273 )),
274 L2NBanks = banks
275 ))
276})
277
278class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
279 case SoCParamsKey =>
280 val sets = n * 1024 / banks / ways / 64

--- 62 unchanged lines hidden --- 		269 )),
270 L2NBanks = banks
271 ))
272})
273
274class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
275 case SoCParamsKey =>
276 val sets = n * 1024 / banks / ways / 64

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