Configs.scala (8882eb685de93177da606ee717b5ec8e459a768a) Configs.scala (4b2c87ba1d7965f6f2b0a396be707a6e2f6fb345)
1/***************************************************************************************
2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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32import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
33import xiangshan.cache.DCacheParameters
34import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
35import device.EnableJtag
36import huancun._
37import coupledL2._
38import coupledL2.prefetch._
39
1/***************************************************************************************
2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

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32import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
33import xiangshan.cache.DCacheParameters
34import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
35import device.EnableJtag
36import huancun._
37import coupledL2._
38import coupledL2.prefetch._
39
40class BaseConfig(n: Int) extends Config((site, here, up) => {
40class BaseConfig(n: Int, hasMbist:Boolean = false) extends Config((site, here, up) => {
41 case XLen => 64
42 case DebugOptionsKey => DebugOptions()
43 case SoCParamsKey => SoCParameters()
44 case CVMParamskey => CVMParameters()
45 case PMParameKey => PMParameters()
41 case XLen => 64
42 case DebugOptionsKey => DebugOptions()
43 case SoCParamsKey => SoCParameters()
44 case CVMParamskey => CVMParameters()
45 case PMParameKey => PMParameters()
46 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
46 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i, hasMbist = hasMbist) }
47 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
48 case DebugModuleKey => Some(DebugModuleParams(
49 nAbstractDataWords = (if (site(XLen) == 32) 1 else if (site(XLen) == 64) 2 else 4),
50 maxSupportedSBAccess = site(XLen),
51 hasBusMaster = true,
52 baseAddress = BigInt(0x38020000),
53 nScratch = 2,
54 crossingHasSafeReset = false,

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66// * L3 cache included
67class MinimalConfig(n: Int = 1) extends Config(
68 new BaseConfig(n).alter((site, here, up) => {
69 case XSTileKey => up(XSTileKey).map(
70 p => p.copy(
71 DecodeWidth = 6,
72 RenameWidth = 6,
73 RobCommitWidth = 8,
47 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
48 case DebugModuleKey => Some(DebugModuleParams(
49 nAbstractDataWords = (if (site(XLen) == 32) 1 else if (site(XLen) == 64) 2 else 4),
50 maxSupportedSBAccess = site(XLen),
51 hasBusMaster = true,
52 baseAddress = BigInt(0x38020000),
53 nScratch = 2,
54 crossingHasSafeReset = false,

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66// * L3 cache included
67class MinimalConfig(n: Int = 1) extends Config(
68 new BaseConfig(n).alter((site, here, up) => {
69 case XSTileKey => up(XSTileKey).map(
70 p => p.copy(
71 DecodeWidth = 6,
72 RenameWidth = 6,
73 RobCommitWidth = 8,
74 FetchWidth = 4,
74 // FetchWidth = 4, // NOTE: make sure that FTQ SRAM width is not a prime number bigger than 256.
75 VirtualLoadQueueSize = 24,
76 LoadQueueRARSize = 24,
77 LoadQueueRAWSize = 12,
78 LoadQueueReplaySize = 24,
79 LoadUncacheBufferSize = 8,
80 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
81 RollbackGroupSize = 8,
82 StoreQueueSize = 20,

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452 new WithFuzzer
453 ++ new DefaultConfig(1)
454)
455
456class DefaultConfig(n: Int = 1) extends Config(
457 L3CacheConfig("16MB", inclusive = false, banks = 4, ways = 16)
458 ++ L2CacheConfig("1MB", inclusive = true, banks = 4)
459 ++ WithNKBL1D(64, ways = 4)
75 VirtualLoadQueueSize = 24,
76 LoadQueueRARSize = 24,
77 LoadQueueRAWSize = 12,
78 LoadQueueReplaySize = 24,
79 LoadUncacheBufferSize = 8,
80 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
81 RollbackGroupSize = 8,
82 StoreQueueSize = 20,

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452 new WithFuzzer
453 ++ new DefaultConfig(1)
454)
455
456class DefaultConfig(n: Int = 1) extends Config(
457 L3CacheConfig("16MB", inclusive = false, banks = 4, ways = 16)
458 ++ L2CacheConfig("1MB", inclusive = true, banks = 4)
459 ++ WithNKBL1D(64, ways = 4)
460 ++ new BaseConfig(n)
460 ++ new BaseConfig(n, true)
461)
462
463class CVMConfig(n: Int = 1) extends Config(
464 new CVMCompile
465 ++ new DefaultConfig(n)
466)
467
468class CVMTestConfig(n: Int = 1) extends Config(

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462
463class CVMConfig(n: Int = 1) extends Config(
464 new CVMCompile
465 ++ new DefaultConfig(n)
466)
467
468class CVMTestConfig(n: Int = 1) extends Config(

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