Configs.scala (586d5e3d059011468417ef1e73d4f787f478cb14) Configs.scala (b280e436fa819716134eee64a45ffba44a91f704)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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21import xiangshan._
22import utils._
23import utility._
24import system._
25import org.chipsalliance.cde.config._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
27import xiangshan.frontend.icache.ICacheParameters
28import freechips.rocketchip.devices.debug._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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21import xiangshan._
22import utils._
23import utility._
24import system._
25import org.chipsalliance.cde.config._
26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
27import xiangshan.frontend.icache.ICacheParameters
28import freechips.rocketchip.devices.debug._
29import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
30import system._
31import utility._
32import utils._
33import huancun._
34import xiangshan._
29import freechips.rocketchip.tile.MaxHartIdBits
35import xiangshan.backend.dispatch.DispatchParameters
30import xiangshan.backend.dispatch.DispatchParameters
36import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
31import xiangshan.backend.exu.ExuParameters
37import xiangshan.cache.DCacheParameters
38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
39import device.{EnableJtag, XSDebugModuleParams}
40import huancun._
41import coupledL2._
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
34import device.{EnableJtag, XSDebugModuleParams}
35import huancun._
36import coupledL2._
42import xiangshan.frontend.icache.ICacheParameters
43
44class BaseConfig(n: Int) extends Config((site, here, up) => {
45 case XLen => 64
46 case DebugOptionsKey => DebugOptions()
47 case SoCParamsKey => SoCParameters()
48 case PMParameKey => PMParameters()
49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))

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57// Synthesizable minimal XiangShan
58// * It is still an out-of-order, super-scalaer arch
59// * L1 cache included
60// * L2 cache NOT included
61// * L3 cache included
62class MinimalConfig(n: Int = 1) extends Config(
63 new BaseConfig(n).alter((site, here, up) => {
64 case XSTileKey => up(XSTileKey).map(
37
38class BaseConfig(n: Int) extends Config((site, here, up) => {
39 case XLen => 64
40 case DebugOptionsKey => DebugOptions()
41 case SoCParamsKey => SoCParameters()
42 case PMParameKey => PMParameters()
43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG))

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51// Synthesizable minimal XiangShan
52// * It is still an out-of-order, super-scalaer arch
53// * L1 cache included
54// * L2 cache NOT included
55// * L3 cache included
56class MinimalConfig(n: Int = 1) extends Config(
57 new BaseConfig(n).alter((site, here, up) => {
58 case XSTileKey => up(XSTileKey).map(
65 _.copy(
66 DecodeWidth = 6,
67 RenameWidth = 6,
68 CommitWidth = 6,
59 p => p.copy(
60 DecodeWidth = 2,
61 RenameWidth = 2,
62 CommitWidth = 2,
69 FetchWidth = 4,
63 FetchWidth = 4,
70 VirtualLoadQueueSize = 24,
64 IssQueSize = 8,
65 NRPhyRegs = 64,
66 VirtualLoadQueueSize = 16,
71 LoadQueueRARSize = 16,
72 LoadQueueRAWSize = 12,
67 LoadQueueRARSize = 16,
68 LoadQueueRAWSize = 12,
73 LoadQueueReplaySize = 24,
69 LoadQueueReplaySize = 12,
74 LoadUncacheBufferSize = 8,
75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
76 RollbackGroupSize = 8,
70 LoadUncacheBufferSize = 8,
71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
72 RollbackGroupSize = 8,
77 StoreQueueSize = 20,
73 StoreQueueSize = 12,
78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
79 StoreQueueForwardWithMask = true,
74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
75 StoreQueueForwardWithMask = true,
80 RobSize = 48,
81 RabSize = 96,
76 RobSize = 32,
82 FtqSize = 8,
77 FtqSize = 8,
83 IBufSize = 24,
84 IBufNBank = 6,
78 IBufSize = 16,
79 IBufNBank = 2,
85 StoreBufferSize = 4,
86 StoreBufferThreshold = 3,
80 StoreBufferSize = 4,
81 StoreBufferThreshold = 3,
87 IssueQueueSize = 8,
88 IssueQueueCompEntrySize = 4,
82 LoadPipelineWidth = 2,
83 StorePipelineWidth = 2,
89 dpParams = DispatchParameters(
90 IntDqSize = 12,
91 FpDqSize = 12,
92 LsDqSize = 12,
84 dpParams = DispatchParameters(
85 IntDqSize = 12,
86 FpDqSize = 12,
87 LsDqSize = 12,
93 IntDqDeqWidth = 8,
88 IntDqDeqWidth = 4,
94 FpDqDeqWidth = 4,
89 FpDqDeqWidth = 4,
95 LsDqDeqWidth = 6
90 LsDqDeqWidth = 4
96 ),
91 ),
97 intPreg = IntPregParams(
98 numEntries = 64,
99 numRead = None,
100 numWrite = None,
92 exuParameters = ExuParameters(
93 JmpCnt = 1,
94 AluCnt = 2,
95 MulCnt = 0,
96 MduCnt = 1,
97 FmacCnt = 1,
98 FmiscCnt = 1,
99 FmiscDivSqrtCnt = 0,
100 LduCnt = 2,
101 StuCnt = 2
101 ),
102 ),
102 vfPreg = VfPregParams(
103 numEntries = 160,
104 numRead = Some(14),
105 numWrite = None,
106 ),
107 icacheParameters = ICacheParameters(
108 nSets = 64, // 16KB ICache
109 tagECC = Some("parity"),
110 dataECC = Some("parity"),
111 replacer = Some("setplru"),
112 nMissEntries = 2,
113 nReleaseEntries = 1,
114 nProbeEntries = 2,

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144 ),
145 sttlbParameters = TLBParameters(
146 name = "sttlb",
147 NWays = 4,
148 partialStaticPMP = true,
149 outsideRecvFlush = true,
150 outReplace = false
151 ),
103 icacheParameters = ICacheParameters(
104 nSets = 64, // 16KB ICache
105 tagECC = Some("parity"),
106 dataECC = Some("parity"),
107 replacer = Some("setplru"),
108 nMissEntries = 2,
109 nReleaseEntries = 1,
110 nProbeEntries = 2,

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140 ),
141 sttlbParameters = TLBParameters(
142 name = "sttlb",
143 NWays = 4,
144 partialStaticPMP = true,
145 outsideRecvFlush = true,
146 outReplace = false
147 ),
152 hytlbParameters = TLBParameters(
153 name = "hytlb",
154 NWays = 4,
155 partialStaticPMP = true,
156 outsideRecvFlush = true,
157 outReplace = false
158 ),
159 pftlbParameters = TLBParameters(
160 name = "pftlb",
161 NWays = 4,
162 partialStaticPMP = true,
163 outsideRecvFlush = true,
164 outReplace = false
165 ),
166 btlbParameters = TLBParameters(

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175 l3nWays = 8,
176 spSize = 2,
177 ),
178 L2CacheParamsOpt = Some(L2Param(
179 name = "L2",
180 ways = 8,
181 sets = 128,
182 echoField = Seq(huancun.DirtyField()),
148 pftlbParameters = TLBParameters(
149 name = "pftlb",
150 NWays = 4,
151 partialStaticPMP = true,
152 outsideRecvFlush = true,
153 outReplace = false
154 ),
155 btlbParameters = TLBParameters(

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164 l3nWays = 8,
165 spSize = 2,
166 ),
167 L2CacheParamsOpt = Some(L2Param(
168 name = "L2",
169 ways = 8,
170 sets = 128,
171 echoField = Seq(huancun.DirtyField()),
183 prefetch = None
184 )),
172 prefetch = None,
173 clientCaches = Seq(L1Param(
174 "dcache",
175 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt
176 )),
177 )
178 ),
185 L2NBanks = 2,
186 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher
187 )
188 )
189 case SoCParamsKey =>
190 val tiles = site(XSTileKey)
191 up(SoCParamsKey).copy(
192 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(

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254 name = "L2",
255 ways = ways,
256 sets = l2sets,
257 clientCaches = Seq(L1Param(
258 "dcache",
259 sets = 2 * p.dcacheParametersOpt.get.nSets / banks,
260 ways = p.dcacheParametersOpt.get.nWays + 2,
261 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt,
179 L2NBanks = 2,
180 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher
181 )
182 )
183 case SoCParamsKey =>
184 val tiles = site(XSTileKey)
185 up(SoCParamsKey).copy(
186 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(

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248 name = "L2",
249 ways = ways,
250 sets = l2sets,
251 clientCaches = Seq(L1Param(
252 "dcache",
253 sets = 2 * p.dcacheParametersOpt.get.nSets / banks,
254 ways = p.dcacheParametersOpt.get.nWays + 2,
255 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt,
262 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes))
256 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)),
257 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt
263 )),
264 reqField = Seq(utility.ReqSourceField()),
265 echoField = Seq(huancun.DirtyField()),
266 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()),
267 enablePerf = !site(DebugOptionsKey).FPGAPlatform,
258 )),
259 reqField = Seq(utility.ReqSourceField()),
260 echoField = Seq(huancun.DirtyField()),
261 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()),
262 enablePerf = !site(DebugOptionsKey).FPGAPlatform,
263 enableRollingDB = site(DebugOptionsKey).EnableRollingDB,
264 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB,
268 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform
269 )),
270 L2NBanks = banks
271 ))
272})
273
274class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
275 case SoCParamsKey =>

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266 )),
267 L2NBanks = banks
268 ))
269})
270
271class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
272 case SoCParamsKey =>

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