SoC.scala (cac098b457095a5d9bdf69be79941e4b41de996b) SoC.scala (59239bc96a73f430bbcce1d2e7f46fb72ed68048)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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78
79class ILABundle extends Bundle {}
80
81
82abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
83 val bankedNode = BankBinder(L3NBanks, L3BlockSize)
84 val peripheralXbar = TLXbar()
85 val l3_xbar = TLXbar()
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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78
79class ILABundle extends Bundle {}
80
81
82abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
83 val bankedNode = BankBinder(L3NBanks, L3BlockSize)
84 val peripheralXbar = TLXbar()
85 val l3_xbar = TLXbar()
86 val l3_banked_xbar = BankedXbar(tiles.head.L2NBanks)
86 val l3_banked_xbar = TLXbar()
87}
88
89// We adapt the following three traits from rocket-chip.
90// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
91trait HaveSlaveAXI4Port {
92 this: BaseSoC =>
93
94 val idBits = 14

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197 supportsRead = TransferSizes(1, 8),
198 supportsWrite = TransferSizes(1, 8),
199 interleavedId = Some(0)
200 ), uartParams),
201 beatBytes = 8
202 )))
203
204 peripheralNode :=
87}
88
89// We adapt the following three traits from rocket-chip.
90// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
91trait HaveSlaveAXI4Port {
92 this: BaseSoC =>
93
94 val idBits = 14

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197 supportsRead = TransferSizes(1, 8),
198 supportsWrite = TransferSizes(1, 8),
199 interleavedId = Some(0)
200 ), uartParams),
201 beatBytes = 8
202 )))
203
204 peripheralNode :=
205 AXI4Buffer() :=
206 AXI4Buffer() :=
205 AXI4UserYanker() :=
206 AXI4Deinterleaver(8) :=
207 TLToAXI4() :=
208 peripheralXbar
209
210 val peripheral = InModuleBody {
211 peripheralNode.makeIOs()
212 }

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234
235 for(port <- peripheral_ports) {
236 peripheralXbar := TLBuffer.chainNode(1, Some("L2_to_L3_peripheral_buffer")) := port
237 }
238
239 for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
240 l3_banked_xbar :=*
241 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=*
207 AXI4UserYanker() :=
208 AXI4Deinterleaver(8) :=
209 TLToAXI4() :=
210 peripheralXbar
211
212 val peripheral = InModuleBody {
213 peripheralNode.makeIOs()
214 }

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236
237 for(port <- peripheral_ports) {
238 peripheralXbar := TLBuffer.chainNode(1, Some("L2_to_L3_peripheral_buffer")) := port
239 }
240
241 for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
242 l3_banked_xbar :=*
243 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=*
242 TLEdgeBuffer(idx => {
243 /*
244 Core0 Core1
245 _____________________________
246 | L3 B0, B2 B1,B3 |
247 -----------------------------
248
249 Core(i) 0 1
250 Port(idx) 0 1 0 1
251 Buffer? N Y Y N
252 */
253 val insert_buffer = (i % 2) != (idx % 2)
254 insert_buffer
255 }, Some(s"core_${i}_to_l3_buffer")) :=* core_out
244 TLBuffer() :=
245 core_out
256 }
246 }
257 l3_banked_xbar :=* BankBinder(tiles.head.L2NBanks, L3BlockSize) :*= l3_xbar
247 l3_banked_xbar := l3_xbar
258
259 val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
260 clint.node := peripheralXbar
261
262 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
263 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
264 lazy val module = new LazyModuleImp(this){
265 val in = IO(Input(Vec(num, Bool())))

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249 val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
250 clint.node := peripheralXbar
251
252 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
253 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
254 lazy val module = new LazyModuleImp(this){
255 val in = IO(Input(Vec(num, Bool())))

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