SoC.scala (9eca914a2c381db90b7f0721cb4854132181b4b9) SoC.scala (a5b77de44ecd30ff2bbdebcfd07ca41d86e70db9)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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40 PAddrBits: Int = 36,
41 extIntrs: Int = 64,
42 L3NBanks: Int = 4,
43 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
44 name = "L3",
45 level = 3,
46 ways = 8,
47 sets = 2048 // 1MB per bank
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 31 unchanged lines hidden (view full) ---

40 PAddrBits: Int = 36,
41 extIntrs: Int = 64,
42 L3NBanks: Int = 4,
43 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
44 name = "L3",
45 level = 3,
46 ways = 8,
47 sets = 2048 // 1MB per bank
48 ))
48 )),
49 XSTopPrefix: Option[String] = None
49){
50 // L3 configurations
51 val L3InnerBusWidth = 256
52 val L3BlockSize = 64
53 // on chip network configurations
54 val L3OuterBusWidth = 256
55}
56

--- 294 unchanged lines hidden --- 		50){
51 // L3 configurations
52 val L3InnerBusWidth = 256
53 val L3BlockSize = 64
54 // on chip network configurations
55 val L3OuterBusWidth = 256
56}
57

--- 294 unchanged lines hidden ---