SoC.scala (1bf9a05a3d43e4022922573991a2cecba0de2294) SoC.scala (720dd6218ef4045360a23b552db1137cbb6e6e59)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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43 L3NBanks: Int = 4,
44 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45 name = "L3",
46 level = 3,
47 ways = 8,
48 sets = 2048 // 1MB per bank
49 )),
50 XSTopPrefix: Option[String] = None,
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 34 unchanged lines hidden (view full) ---

43 L3NBanks: Int = 4,
44 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45 name = "L3",
46 level = 3,
47 ways = 8,
48 sets = 2048 // 1MB per bank
49 )),
50 XSTopPrefix: Option[String] = None,
51 NodeIDWidth: Int = 7
51 NodeIDWidth: Int = 7,
52 UseXSNoCTop: Boolean = false,
53 IMSICUseTL: Boolean = false
52){
53 // L3 configurations
54 val L3InnerBusWidth = 256
55 val L3BlockSize = 64
56 // on chip network configurations
57 val L3OuterBusWidth = 256
58}
59

--- 359 unchanged lines hidden --- 		54){
55 // L3 configurations
56 val L3InnerBusWidth = 256
57 val L3BlockSize = 64
58 // on chip network configurations
59 val L3OuterBusWidth = 256
60}
61

--- 359 unchanged lines hidden ---